Verilog: elaborate starting from top-level module#1629
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Verilog: elaborate starting from top-level module#1629
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This strengthens the typing when accessing the assignments in verilog_parameter_overridet.
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This changes the type checking for defparam items such that they work without prior type checking of the module for which the parameter is defined.
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This changes the type checking of packages to be done in the order given in the compilation unit. IEEE 1800 2017 26.3 Referencing data in packages: "The compilation of a package shall precede the compilation of scopes in which the package is imported." Hence, there is no need to re-order the elaboration to support use that is out-of-order.
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IEEE 1800-2017 Sec. 23.10.4 suggests an algorithm that defines an order for elaboration; this order starts with the "top-level modules". This commit changes the order of the module elaboration to begin with the top-level module. Modules not instantiated will no longer be elaborated. This enables recursive module definitions.
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IEEE 1800-2017 Sec. 23.10.4 suggests an algorithm that defines an order for elaboration; this order starts with the "top-level modules".
This commit changes the order of the module elaboration to begin with the top-level module. Modules not instantiated will no longer be elaborated.