Skip to content

Commit ecda797

Browse files
committed
Verilog: elaborate starting from top-level module
1 parent def0d19 commit ecda797

File tree

3 files changed

+18
-10
lines changed

3 files changed

+18
-10
lines changed
Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
module_not_found1.v
33
--bound 1 --top main
4-
^found no file that provides module Verilog::some_module_that_does_not_exist$
4+
^file .* line 3: module not found$
55
^EXIT=2$
66
^SIGNAL=0$
77
--

src/verilog/verilog_ebmc_language.cpp

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,7 @@ void verilog_ebmc_languaget::typecheck_module(
150150

151151
module.in_progress = true;
152152

153+
#if 0
153154
// first get dependencies of current module
154155
const auto dependency_set = module.parse_tree.dependencies(module.identifier);
155156

@@ -169,6 +170,7 @@ void verilog_ebmc_languaget::typecheck_module(
169170

170171
typecheck_module(dependency_it->second, symbol_table);
171172
}
173+
#endif
172174

173175
// type check the module
174176
log.status() << "Type-checking " << module.identifier << messaget::eom;
@@ -208,8 +210,11 @@ void verilog_ebmc_languaget::typecheck_module(
208210
module.in_progress = false;
209211
}
210212

213+
#include <iostream>
214+
211215
transition_systemt verilog_ebmc_languaget::typecheck(
212216
const parse_treest &parse_trees,
217+
irep_idt top_level_module,
213218
symbol_tablet &&symbol_table)
214219
{
215220
// set up the module map
@@ -230,9 +235,12 @@ transition_systemt verilog_ebmc_languaget::typecheck(
230235

231236
transition_system.symbol_table = std::move(symbol_table);
232237

233-
for(auto &[_, module] : module_map)
238+
for(auto &[id, module] : module_map)
234239
{
235-
typecheck_module(module, transition_system.symbol_table);
240+
if(id == verilog_module_symbol(top_level_module))
241+
{
242+
typecheck_module(module, transition_system.symbol_table);
243+
}
236244
}
237245

238246
return transition_system;
@@ -486,25 +494,25 @@ std::optional<transition_systemt> verilog_ebmc_languaget::transition_system()
486494
for(auto &parse_tree : parse_trees)
487495
copy_parse_tree(parse_tree, symbol_table);
488496

497+
//
498+
// determine the top-level module
499+
//
500+
auto top_level_module = this->top_level_module(parse_trees);
501+
489502
//
490503
// type checking
491504
//
492505

493506
message.status() << "Converting" << messaget::eom;
494507

495-
auto transition_system = typecheck(parse_trees, std::move(symbol_table));
508+
auto transition_system = typecheck(parse_trees, top_level_module, std::move(symbol_table));
496509

497510
if(cmdline.isset("show-symbol-table"))
498511
{
499512
std::cout << transition_system.symbol_table;
500513
return {};
501514
}
502515

503-
//
504-
// determine the top-level module
505-
//
506-
auto top_level_module = this->top_level_module(parse_trees);
507-
508516
if(get_main(top_level_module, message_handler, transition_system))
509517
throw ebmc_errort{}.with_exit_code(1);
510518

src/verilog/verilog_ebmc_language.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ class verilog_ebmc_languaget : public ebmc_languaget
6767

6868
std::map<irep_idt, modulet> module_map;
6969

70-
transition_systemt typecheck(const parse_treest &, symbol_tablet &&);
70+
transition_systemt typecheck(const parse_treest &, irep_idt top_level_module, symbol_tablet &&);
7171
void typecheck_module(modulet &, symbol_tablet &);
7272
};
7373

0 commit comments

Comments
 (0)