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Verilog: use separate symbol for module source #1628

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Merged
tautschnig merged 1 commit into from
Feb 6, 2026

Verilog: use separate symbol for module source

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Merged

Verilog: use separate symbol for module source #1628

Verilog: use separate symbol for module source
7a11da6
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succeeded Feb 5, 2026 in 1m 30s