Verilog: use separate symbol for module source#1628
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tautschnig merged 1 commit intomainfrom Feb 6, 2026
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Instead of attaching the source of a module to the type of the symbol for the default-parameterized module, use a separate (suffix $source) symbol.
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Instead of attaching the source of a module to the type of the symbol for the default-parameterized module, use a separate (suffix $source) symbol.