Interfaced De0 Nano FPGA Board using Quartus Prime and Verilog with a TCS3200 Color Sensor, UART with HC05 Bluetooth module, and Line Following Array. Moreover, a single cycle RV321 ISA RISC-V CPU was implemented in order to execute a low memory (256 Bytes) pathfinding algorithm for IIT-B's eYantra Competition. Moreover, Designed an Enclosure from scratch to neatly accomodate the FPGA and sensors, while carefully considering factors such as Center of Mass and Light Leak protection for LFA and Color Detection Sensors.
