Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board

Computer Architecture -VLSI -Verilog Codes-Xilinx-Irsim

Toolkit for collecting and exploring logs using pipelined query lanaguage and sqlite.

Oracle Advanced PL/SQL

This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.

Cached 5-stage Pipelined RV32I Processor (Team 19). Supports full RV32I base instructions and features a 2-way set-associative data cache. Highest verified milestone (Stretch Goals 1, 2, 3).