Keccak Message Authentication Code (KMAC) and Secure Hashing Algorithm 3 (SHA3)

Debugging in RISC-V can be done using one of the following mechanisms:

OpenTitan Prim Xilinx IP block

OpenTitan Rv Core Ibex IP block

ROM controller (rom_ctrl) is the connection between the chip and its ROM

The mailbox IP block in the OpenTitan Integrated design implements a request-response channel that the host System-on-Chip (SoC) may use to request security ser

OpenTitan Flash Ctrl IP block

SRAM memory controller

Entropy Distribution Network (EDN) interfaces to the CSRNG IP module

OpenTitan Key Manager

Primitives - low-level reuseable components

Always-On ("AON") Timer

System Reset Controller (sysrst_ctrl) that provides programmable hardware-level responses to trusted IOs and basic board-level reset sequencing capabilities

Cryptographically Secure Random Number Generator (CSRNG)

I2C controller

OpenTitan Prim Generic IP block

Analog to Digital Converter Control Interface

This document specifies the OTP MACRO hardware IP functionality.

Entropy Source: interface to an external physical random noise generator

RISC-V Debug System wrapper functionality