Arbiter PUF on FPGA

Implementation of an Arbiter Physical Unclonable Function (PUF) in Verilog, developed as part of my Bachelor's thesis in Computer Science.

The project explores the design, implementation, and testing of an Arbiter PUF on an FPGA platform, focusing on its properties as a hardware security primitive for applications such as device authentication and cryptographic key generation.

Repository structure

• Code source
  • Arbiter PUF implementation
  • Arbiter PUF evaluation
    • Data extrapolated
    • Script to build plots
• Documents
  • Thesis PDF
  • Slides on HDL for IoT course

Tools

• Vivado: Software suite for synthesis of hardware description language designs (HDL).
• Nexys A7: FPGA board
• Verilog: HDL language to implement PUF design
• Python: to calculate the metrics to evaluate PUF