Skip to content

adding behavioral_verilog to system_cadence_genus.mk #369

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Merged
ruck314 merged 2 commits into from
Feb 4, 2026
Merged

adding behavioral_verilog to system_cadence_genus.mk #369

ruck314 merged 2 commits into from
Feb 4, 2026

Conversation

@ruck314
Copy link
Contributor

@ruck314 ruck314 commented Feb 4, 2026

Description

  • Useful if you need convert a project worth of mixed-language or VHDL into Verilog

@ruck314 ruck314 merged commit 6a899e3 into pre-release Feb 4, 2026
2 checks passed
@ruck314 ruck314 mentioned this pull request Feb 4, 2026
Merged
@ruck314 ruck314 deleted the export_behavioral branch February 4, 2026 17:25
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.

1 participant

@ruck314