Enable ICE clock scaling#927
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arakshit011 wants to merge 6 commits intoqualcomm-linux:tech/security/icefrom
Open
Enable ICE clock scaling#927arakshit011 wants to merge 6 commits intoqualcomm-linux:tech/security/icefrom
arakshit011 wants to merge 6 commits intoqualcomm-linux:tech/security/icefrom
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…for QCOM ICE Add support for specifying OPPs for the Qualcomm Inline Crypto Engine by allowing the use of the standard "operating-points-v2" property in the ICE device node. ICE clock management was handled by the storage drivers in legacy bindings, so the ICE driver itself had no mechanism for clock scaling. With the introduction of the new standalone ICE device node, clock control must now be performed directly by the ICE driver. Enabling operating-points-v2 allows the driver to describe and manage the frequency and voltage requirements for proper DVFS operation. Link: https://lore.kernel.org/all/20260219-enable-ufs-ice-clock-scaling-v6-1-0c5245117d45@oss.qualcomm.com/ Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Register optional operation-points-v2 table for ICE device during device probe. Attach the OPP-table with only the ICE core clock. Since, dtbinding is on a trasition phase to include iface clock and clock-names, attaching the opp-table to core clock remains options such that it does not cause probe failures. Introduce clock scaling API qcom_ice_scale_clk which scale ICE core clock based on the target frequency provided and if a valid OPP-table is registered. Use round_ceil passed to decide on the rounding of the clock freq against OPP-table. Clock scaling is disabled when a valid OPP-table is not registered. This ensures when an ICE-device specific OPP table is available, use the PM OPP framework to manage frequency scaling and maintain proper power-domain constraints. Also, ensure to drop the votes in suspend to prevent power/thermal retention. Subsequently restore the frequency in resume from core_clk_freq which stores the last ICE core clock operating frequency. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-1-ca1129798606@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
Implement ICE (Inline Crypto Engine) clock scaling in sync with UFS controller clock scaling. This ensures that the ICE operates at an appropriate frequency when the UFS clocks are scaled up or down, improving performance and maintaining stability for crypto operations. For scale_up operation ensure to pass ~round_ceil (round_floor) and vice-versa for scale_down operations. Incase of OPP scaling is not supported by ICE, ensure to not prevent devfreq for UFS, as ICE OPP-table is optional. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-2-ca1129798606@oss.qualcomm.com/ Acked-by: Manivannan Sadhasivam <mani@kernel.org> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
MMC controller lacks a clock scaling mechanism, unlike the UFS controller. By default, the MMC controller is set to TURBO mode during probe, but the ICE clock remains at XO frequency, leading to read/write performance degradation on eMMC. To address this, set the ICE clock to TURBO during sdhci_msm_ice_init to align it with the controller clock. This ensures consistent performance and avoids mismatches between the controller and ICE clock frequencies. For platforms where ICE is represented as a separate device, use the OPP framework to vote for TURBO mode, maintaining proper voltage and power domain constraints. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-3-ca1129798606@oss.qualcomm.com/ Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… eMMC nodes Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE eMMC device nodes for Kodiak platform. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-4-ca1129798606@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
… eMMC nodes Qualcomm Inline Crypto Engine (ICE) platform driver now, supports an optional OPP-table. Add OPP-table for ICE UFS and ICE eMMC device nodes for Monaco platform. Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-5-ca1129798606@oss.qualcomm.com/ Signed-off-by: Abhinaba Rakshit <abhinaba.rakshit@oss.qualcomm.com>
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Introduce support for dynamic clock scaling of the ICE (Inline Crypto Engine)
using the OPP framework. During ICE device probe, the driver now attempts to
parse an optional OPP table from the ICE-specific device tree node for
DVFS-aware operations. API qcom_ice_scale_clk is exposed by ICE driver
and is invoked by UFS host controller driver in response to clock scaling
requests, ensuring coordination between ICE and host controller.
For MMC controllers that do not support clock scaling, the ICE clock frequency
is kept aligned with the MMC controller’s clock rate (TURBO) to ensure
consistent operation.
Dynamic clock scaling based on OPP tables enables better power-performance
trade-offs. By adjusting ICE clock frequencies according to workload and power
constraints, the system can achieve higher throughput when needed and
reduce power consumption during idle or low-load conditions.
The OPP table remains optional, absence of the table will not cause
probe failure. However, in the absence of an OPP table, ICE clocks will
remain at their default rates, which may limit performance under
high-load scenarios or prevent performance optimizations during idle periods.
Testing:
Link: https://lore.kernel.org/all/20260409-enable-ice-clock-scaling-v8-0-ca1129798606@oss.qualcomm.com/
Signed-off-by: Abhinaba Rakshit abhinaba.rakshit@oss.qualcomm.com