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media: iris: add support for purwa platform #914

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media: iris: add support for purwa platform #914

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db53347
FROMLIST: arm64: dts: qcom: purwa: Override Iris clocks and operating…
Jan 22, 2026
b915a2e
FROMLIST: arm64: dts: qcom: purwa-iot-som: enable video
Jan 22, 2026
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4 changes: 4 additions & 0 deletions arch/arm64/boot/dts/qcom/purwa-iot-som.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -389,6 +389,10 @@
firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
};

&iris {
status = "okay";
};

&pcie3 {
pinctrl-0 = <&pcie3_default>;
pinctrl-names = "default";
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50 changes: 50 additions & 0 deletions arch/arm64/boot/dts/qcom/purwa.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
/delete-node/ &cpu_pd11;
/delete-node/ &gpu_opp_table;
/delete-node/ &gpu_speed_bin;
/delete-node/ &iris_opp_table;
/delete-node/ &pcie3_phy;
/delete-node/ &thermal_zones;
/delete-node/ &etm8;
Expand Down Expand Up @@ -165,6 +166,55 @@
compatible = "qcom,x1p42100-gpucc";
};

&iris {
compatible = "qcom,x1p42100-iris";

clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>,
<&videocc VIDEO_CC_MVS0_BSE_CLK>;
clock-names = "iface",
"core",
"vcodec0_core",
"vcodec0_bse";

operating-points-v2 = <&iris_opp_table_x1p42100>;

iris_opp_table_x1p42100: opp-table {
compatible = "operating-points-v2";

opp-210000000 {
opp-hz = /bits/ 64 <210000000 105000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>,
<&rpmhpd_opp_low_svs>;
};

opp-300000000 {
opp-hz = /bits/ 64 <300000000 150000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>,
<&rpmhpd_opp_svs>;
};

opp-335000000 {
opp-hz = /bits/ 64 <335000000 167500000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs_l1>;
};

opp-424000000 {
opp-hz = /bits/ 64 <424000000 212000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_nom>;
};

opp-500000000 {
opp-hz = /bits/ 64 <500000000 250000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_turbo>;
};
};
};

/* PCIe3 has half the lanes compared to X1E80100 */
&pcie3 {
num-lanes = <4>;
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