Adding draft of PCB Layout and updated schematic

[sdutta21]

No description provided.

[coreyacl]

Feedback for layout:

1. Make your second layer (Back layer) a GND pour (Right panel -> Add Fill Zone) It'll make dealing with GND a lot easier
2. Go to File > Board Setup > Design Rules | And adjust them according to this Confluence page: https://docs.olinelectricmotorsports.com/display/RES/KiCAD+Tutorial
3. Avoid making loops with your traces. Loops invite parasitic inductance due to it's geometric shape, and it invites parasitic capacitance due to it's physical proximity with other traces/copper (See R10 & R14 traces AND J1&J2 GND path)
4. Try routing GND last
5. There is no obvious or clear way to get the battery connection to the IC at the moment. Try routing large currents first. So everything in the battery -> charging path
6. There is no obvious or clear way to get the Micro USB connection to the IC. Same as comment 5.
7. Move connectors to the edge of the PCB in order to make it easier to use. Look at 3D view to help you with the placement.
8. Move the fuse (F1) so as to minimize trace length. More trace length = more trace resistance = more heat generated
9. You have text in the F.Cu (front copper plane) which should be in the F.SilkS (silkscreen) layer. For two reasons: It's harder to read copper text AND you don't want to electrically floating copper islands which could encourage EMI.
10. Once you have the second layer you can start using vias (drilled holes) to hope around necessary traces. You want to avoid vias as much possible, but when you do use them make them as short as possible.

[coreyacl]

Nice work on your second pass!

1. Don't forget to run the DRC (little laybug) before submitting work for review or a PR. You had some out of date copper pours that needed to be filled and it revealed a couple of (resolvable) errors. The DRC is showing courtyard overlaps. The courtyard is the outline of the physical space that the component takes up. (Grey line on most parts). If they're overlapping, that means the physical components will probably overlap as well.
2. For GND, since you have a ground plane on your second (bottom) layer you can easily drop a via for all of your GND connections. To do that you can manually add a via on the right, or you can simply press 'V' when you're in routing mode. Press 'X' to enter routing mode, click on a GND pad, move your mouse slightly away from the pad, then press 'V' to drop a via. Press escape to exit routing mode and viola, you've dropped a GND via! Make sure not to drop a via INSIDE a pad, that costs more money.
3. As discussed during the meeting, I recommend using copper pours for all of the battery/charge nets.
4. There are some Vbus nets that have not been routed yet.
5. Make sure your board outline is in the "Edge.Cuts" layer. This is to ensure that the PCB manufacturer knows exactly which shape corresponds to the board outline.
6. It looks like you're using the wrong Micro-USB connector. I believe the right one is called "USB-Micro-1981..."
7. This PCB is probably going to be mounted to some structure in the future, totally up to you, so you may want to place both USB connectors in the same spot so you don't have to worry about carving out two holes instead of one. You probably want both JST connectors on the same side though so that you're battery/thermistor isn't hanging off the same side as your USB connector.
8. Remove "TP" silkscreen, instead label what NET it's connected to
9. I think you can tidy the silkscreen a bit. Your arrow to the collection of silkscreen is rather confusing. Took me a minute to figure out what was happening
10. C5 isn't routed.
11. C2 is supposed to offer capacitance to the micro USB but is nowhere near it.
12. C3 and C4 should be closer to U3.
13. Same with C7. Feel free to shift the resistors in order to prioritize the caps.
14. Power LED seems to be labeling a different LED that isn't the actual power LED.
15. I think you can afford to move the USB connectors closer to the edge (if not slightly off of it) for a better connection
16. Don't forget to add the following silkscreen: Board name (new line) "Olin Electric Motorsports" (New Line) mm/yy (New Line) Name

[coreyacl]

1. Nice copper planes. I would recommend trying to get the planes to overlap with their respective pins so that you don't bottleneck the current with a teeny 6-mil trace. Same goes with the current going through the fuse. Planes all the way.
2. You're bottlenecking your right-half board GND with a single via. They are technically electrically connected, but rather poorly through 1 via. It's fine for one component, less so for half a board. You could add more vias or consider stretching the GND plane across the entire bottom side of the board. (you can leave that little patch of Vbus if you want)
3. A trick I picked up from a coworker last summer: Add copper planes around your USB pads so that it takes more mechanical force to pry them off the board.
4. For that unconnected pin, you can drop a via to get there since you have a relatively clean GND plane as is, which means you can afford a couple traces through the GNDplane.
5. I haven't mentioned this before, but you definitely want planes for the inductor connections. You might be able to simply turn L1 90 degrees counter-clockwise to have it fit nicely with the plane that's currently there. But you should still add a plane from the pin to the inductor.
6. Recall that a capacitor loses it's effectivness in filtering the further away it is from the device it's trying to filter FOR. I think you can definitely move all of the capacitors closer (aside from C5, C5 is nice)
   Great job so far! It's starting to look like a professional board! 🦜

[coreyacl]

OH also. you might want to consider moving the USBA connector a bit closer onto the board for mechanical sturdiness.

[coreyacl]

1. I like the via squad (3x3) but I would spread those out a little more and have the same vias simply spread further towards the edges of the copper pour they're in.
2. Please wrap the GND plane all around the board. Electrons flow from GND to Vbat, and you have a tiny 6mil trace connecting the GND of the battery to the rest of the board.
3. Half of your vias in the via squad aren't connected to Vbus on the second layer.
4. You can move L1 closer to the IC. Prioritize component placement, no silksreen placement.
5. You can make the current loop tighter with C6. Connect 5V pad directly to the IC (keep the copper pour too!)
6. Where are your designators for your two ICs?
7. The right IC is connected to GND with a single via. Add more vias around R10 and R14.
8. Refer to comment 3 in the above Github comment. (About the USB copper pours)
9. Try and see if you can move the large USB connector more on board. Think about how this might look if it were inside an altoids tin. The USB A connector will be sticking out like a sore thumb, but that' totally up to you since you'll be using it.
   It's looking pretty good!

[coreyacl]

ALSO! Right now you have a 6 mil trace that leaves your battery connector for both Vbat and GND. Either plane those or make them 15 mil traces.