Fix aarch64 page table parsing for 5 level paging#158
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cfernald merged 3 commits intomicrosoft:mainfrom Mar 4, 2026
Merged
Fix aarch64 page table parsing for 5 level paging#158cfernald merged 3 commits intomicrosoft:mainfrom
cfernald merged 3 commits intomicrosoft:mainfrom
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With 2511, the arm mmu library added support for an additional paging level. When this occurs the current debugger logic will underflow and start parsing the page tables with garbage levels and entry counts. This change updates the level calculation to reflect the arm mmu library changes.
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Pull request overview
Updates the AArch64 debugger’s page-table walking logic to account for the Arm MMU library introducing an additional paging level (5-level paging), preventing level calculation underflow that can lead to garbage parsing.
Changes:
- Change the page-table walker’s
TableLeveltype fromUINTNtoINTNto allow representing an extra top level. - Add a guard so
TableLevelbecomes-1whenT0SZ < MIN_T0SZ(5-level paging scenario).
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apop5
approved these changes
Mar 4, 2026
kuqin12
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Mar 4, 2026
os-d
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Mar 4, 2026
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With 2511, the arm mmu library added support for an additional paging level. When this occurs the current debugger logic will underflow and start parsing the page tables with garbage levels and entry counts. This change updates the level calculation to reflect the arm mmu library changes.
Description
With 2511, the arm mmu library added support for an additional paging level. When this occurs the current debugger logic will underflow and start parsing the page tables with garbage levels and entry counts. This change updates the level calculation to reflect the arm mmu library changes.
How This Was Tested
Tested on SBSA initial breakpoint
Integration Instructions
N/A