ot_spi_device Set WEL/BUSY bits in UPLOAD_CMD_FIFO

[amit-kumarh]

When using real silicon in Flash mode, the WEL and BUSY bits corresponding to the command being uploaded are set in the UPLOAD_CMD_FIFO register. This PR matches the behavior in the emulator

[AlexJones0]

Thanks for looking at this, it definitely seems closer to the HW. I have one question - it seems that this PR will set the WEL/BUSY bits based on the current flash status, whereas the docs say that these fields are the state of these flash status bits "at command time". From my interpretation (I haven't looked at the RTL to confirm), that sounds like these bits should also be queued along with the cmd_info in the command fifo in ot_spi_device_flash_try_upload. WDYT?

Aside: most of the CI failures are expected (SPI console in QEMU is currently broken in earlgrey_1.0.0 as a fix was reverted temporarily to get the ATE flow working, see lowRISC/opentitan#29012). There are a couple of unclear failures with the OTP and USBDEV but I imagine these are related to OT test changes because this PR seems unrelated.

[amit-kumarh]

Thanks for the catch, the datasheet definitely implies that and I took a quick peek the RTL and you are correct.

Looks like we only have an 8-bit FIFO at the moment here though - I'll push an update that changes to a 32-bit FIFO and fill in the WEL/BUSY bits?

[AlexJones0]

I'll push an update that changes to a 32-bit FIFO and fill in the WEL/BUSY bits?

That sounds reasonable to me, thanks for looking into this.

[jwnrt]

FYI we've changed the default branch to ot-10.2.0, you may want to retarget your PR

[AlexJones0]

Looks good to me, thanks for the fix!

[AlexJones0]

Nit: if possible, shorten this line to make the formatting nicer? The comment is somewhat stale now, so maybe it could be: /* Command FIFO (see UPLOAD_CMDFIFO) */ or similar?