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1. Verilog-Codes-HDLBits Verilog-Codes-HDLBits Public

   In this repo, I'm documenting some of the interesting programs which I have solved on the hdlbits site https://hdlbits.01xz.net/

   Verilog 1

2. AXI4-Lite-based_Data-Sorter AXI4-Lite-based_Data-Sorter Public

   In this repository, an AXI4-Lite Protocol Slave Peripheral Transaction has been coded that can receive data packets, validate them based on sorting condition valid or invalid storage. The design of…

   JavaScript 1

3. OpenLane_Workshop OpenLane_Workshop Public

   In this repository I have pushed my work, which was updated throughout the workshop on OpenLane and other Open source tools based work on Digital VLSI SoC Design

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4. VSD-RTLDesign_and_Synthesis VSD-RTLDesign_and_Synthesis Public

   This repository documents learnings and lab work from the “RTL Design using Verilog with Sky130 Technology” workshop offered by VLSI System Design.

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5. Advanced-Lane-Lines Advanced-Lane-Lines Public

   Forked from Dt-Pham/Advanced-Lane-Lines

   A pipeline that can detects lane boundaries, predicts upcoming curves, and measures lane curvature.

   Jupyter Notebook

6. RTL-codes RTL-codes Public

   These codes are designed for specific digital ckt.s

   Verilog