Show L3CA/MBA COS definitions per L3 cluster on AMD and Hygon #305
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From Intel RDT spec[1] and AMD Platform QoS spec[2]: If the CPU platform supports CPUID.0FH.01H:EAX, CPUID.0FH.01H:EAX[7:0] returns MBM counter length (width) as offset from 24. But in hw_cap_mon_discover(), the MBM counter length is calculated with incorrect 7-bits bitmask (0x7f). Fix the issue with 8-bits bitmask (0xff) for MBM counter length. [1] Intel Architectures SDM, Vol.3B, 19.18 Intel RDT Monitoring: https://cdrdv2.intel.com/v1/dl/getContent/671200 [2] AMD Platform QoS Extensions, Rev 1.03: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf Fixes: 050f8c6 ("lib: detect MBM counter length") Signed-off-by: Xiaochen Shen <[email protected]>
Hygon CPUs support Platform QoS features (PQoS Version V1.0) described in the AMD Platform QoS specification[1]. Following Platform QoS sub-features are available on Hygon CPUs if the underlying hardware supports it: - L3 Cache Occupancy Monitoring (CMT) - L3 External Memory Bandwidth Monitoring (MBM) - L3 Cache Allocation Enforcement (CAT) - Code and Data Prioritization (CDP) - Memory Bandwidth Enforcement/Allocation (MBA) [1] AMD Platform QoS Extensions, Rev 1.03: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/other/56375_1_03_PUB.pdf Signed-off-by: Xiaochen Shen <[email protected]>
Add PQOS_VENDOR id Python interface for Hygon Platform QoS features. Signed-off-by: Xiaochen Shen <[email protected]>
The default base MBM counter length (width) is 24 bits. Currently, Hygon CPU does not support the CPUID 0xF.[ECX=1]:EAX to adjust the counter length. But the Hygon CPU supports wider counter with the fixed width of 32 bits. Set the default MBM counter length to 32 bit by adjusting the offset to 8 bits for Hygon. Hygon future products will implement CPUID 0xF.[ECX=1]:EAX. Signed-off-by: Xiaochen Shen <[email protected]>
The function pqos_cpu_get_l3_clusters retrieves the L3 cluster id's from cpu info structure. This function will be used in pqos function print_per_l3_cluster_config. Signed-off-by: Xiaochen Shen <[email protected]>
The function print_per_l3_cluster_config prints per L3 cluster L3 CAT, MBA and SMBA class definition. This function will be used in function alloc_print_config. Signed-off-by: Xiaochen Shen <[email protected]>
AMD and Hygon Platform QoS allocation configuration is per L3 cluster
(or Core Complex - CCX). Each L3 cluster (CCX) has one L3 cluster ID
which is used for both CAT and MBA ids.
Show L3CA/MBA COS definitions per L3 cluster instead of per socket on
AMD and Hygon platforms. The output of "pqos -s" looks like:
$ pqos -s
L3CA/MBA COS definitions for L3 Cluster (or Core Complex) 0:
L3CA COS0 => MASK 0xffff
...
L3CA COS15 => MASK 0xffff
MBA COS0 => 2048 available
...
MBA COS15 => 2048 available
L3CA/MBA COS definitions for L3 Cluster (or Core Complex) N:
...
Signed-off-by: Xiaochen Shen <[email protected]>
Author
|
Note: The code base of this PR is on top of #300 and #299 [This PR - #305 ] [PR #300 ] [PR #299 ] Best regards, |
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Show L3CA/MBA COS definitions per L3 cluster on AMD and Hygon
Description
This PR adds 3 patches (2 preparatory patches) to support showing L3CA/MBA COS definitions per L3 cluster instead of per socket on AMD and Hygon platforms that Platform QoS allocation configuration is per L3 cluster (or Core Complex - CCX).
The output of "pqos -s" looks like:
Xiaochen Shen (3):
lib: Introduce pqos_cpu_get_l3_clusters
pqos: Introduce print_per_l3_cluster_config
pqos: Show L3CA/MBA COS definitions per L3 cluster on AMD and Hygon
Affected parts
Motivation and Context
AMD and Hygon Platform QoS allocation configuration is per L3 cluster (or Core Complex - CCX). Each L3 cluster (CCX) has one L3 cluster ID which is used for both CAT and MBA ids.
Show L3CA/MBA COS definitions per L3 cluster instead of per socket on AMD and Hygon platforms. The output of "pqos -s" looks like:
How Has This Been Tested?
(1) The output of "pqos -s" shows "L3CA/MBA COS definitions for L3 Cluster (or Core Complex) N" on AMD or Hygon platforms.
(2) Passed all tests in intel-cmt-cat/unit-test.
Types of changes
Checklist: