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[codegen] Track thumbv7m-none-eabi, riscv32imc-unknown-none-elf#3103

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[codegen] Track thumbv7m-none-eabi, riscv32imc-unknown-none-elf#3103
joshlf wants to merge 2 commits intomainfrom
Gendq4lo5ioqhx5sfxgkq7iza57vwhm6e

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@joshlf joshlf commented Mar 10, 2026


Latest Update: v3 — Compare vs v2

📚 Full Patch History

Links show the diff between the row version and the column version.

Version v2 v1 Base
v3 vs v2 vs v1 vs Base
v2 vs v1 vs Base
v1 vs Base
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Summary of Changes

Hello, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request significantly enhances the project's codegen testing capabilities by integrating two new embedded targets, ARM Cortex-M3 and RISC-V 32-bit. This expansion ensures broader compatibility and performance validation for the zerocopy library across diverse hardware architectures, improving the robustness and reliability of the generated code for embedded systems.

Highlights

  • Expanded Codegen Testing: Introduced codegen tests for two new embedded targets: thumbv7m-none-eabi (ARM Cortex-M3) and riscv32imc-unknown-none-elf (RISC-V 32-bit).
  • Refactored Test Infrastructure: The codegen test suite was refactored to support multiple Instruction Set Architectures (ISAs) by introducing an IsaConfig struct and iterating over defined ISA configurations.
  • New Codegen Benchmarks: Added numerous new assembly output files (.cortex-m3 and .generic-rv32) for various zerocopy operations, providing detailed performance insights for these new targets.
  • Dependency Update: Updated zerocopy_derive imports to zerocopy in benchmark files, reflecting changes in the library's structure.

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Changelog
  • benches/formats/coco_dynamic_padding.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/formats/coco_dynamic_size.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/formats/coco_static_size.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/read_from_bytes.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/read_from_bytes.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/read_from_bytes.x86-64
    • Updated jump labels from .LBB5_2 to .LBB0_2.
  • benches/read_from_bytes.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB0_2 in instruction info and resource pressure sections.
  • benches/read_from_prefix.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/read_from_prefix.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/read_from_prefix.x86-64
    • Updated jump labels from .LBB5_2 to .LBB1_2.
  • benches/read_from_prefix.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB1_2 in instruction info and resource pressure sections.
  • benches/read_from_suffix.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/read_from_suffix.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/read_from_suffix.x86-64
    • Updated jump labels from .LBB5_2 to .LBB2_2.
  • benches/read_from_suffix.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB2_2 in instruction info and resource pressure sections.
  • benches/ref_from_bytes_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_bytes_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_bytes_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_3 to .LBB3_3 and .LBB5_4 to .LBB3_4.
  • benches/ref_from_bytes_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_3 to .LBB3_3 and .LBB5_4 to .LBB3_4 in instruction info and resource pressure sections.
  • benches/ref_from_bytes_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_bytes_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_bytes_dynamic_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB4_2.
  • benches/ref_from_bytes_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB4_2 in instruction info and resource pressure sections.
  • benches/ref_from_bytes_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_bytes_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_bytes_with_elems_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_bytes_with_elems_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_bytes_with_elems_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_5 to .LBB6_5 and .LBB5_3 to .LBB6_5.
  • benches/ref_from_bytes_with_elems_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_5 to .LBB6_5 and .LBB5_3 to .LBB6_5 in instruction info and resource pressure sections.
  • benches/ref_from_bytes_with_elems_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_bytes_with_elems_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_bytes_with_elems_dynamic_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB7_2 and .LBB5_3 to .LBB7_3.
  • benches/ref_from_bytes_with_elems_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB7_2 and .LBB5_3 to .LBB7_3 in instruction info and resource pressure sections.
  • benches/ref_from_prefix_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_prefix_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_prefix_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB8_1 and .LBB5_3 to .LBB8_3.
  • benches/ref_from_prefix_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB8_1 and .LBB5_3 to .LBB8_3 in instruction info and resource pressure sections.
  • benches/ref_from_prefix_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_prefix_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_prefix_dynamic_size.x86-64
    • Updated jump labels from .LBB5_4 to .LBB9_4 and .LBB5_3 to .LBB9_3.
  • benches/ref_from_prefix_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_4 to .LBB9_4 and .LBB5_3 to .LBB9_3 in instruction info and resource pressure sections.
  • benches/ref_from_prefix_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_prefix_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_prefix_with_elems_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_prefix_with_elems_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_prefix_with_elems_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_5 to .LBB11_5 and .LBB5_3 to .LBB11_3 and .LBB5_4 to .LBB11_4.
  • benches/ref_from_prefix_with_elems_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_5 to .LBB11_5, .LBB5_3 to .LBB11_3, and .LBB5_4 to .LBB11_4 in instruction info and resource pressure sections.
  • benches/ref_from_prefix_with_elems_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_prefix_with_elems_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_prefix_with_elems_dynamic_size.x86-64
    • Updated jump labels from .LBB5_1 to .LBB12_1, .LBB5_4 to .LBB12_4, and .LBB5_3 to .LBB12_1.
  • benches/ref_from_prefix_with_elems_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB12_1, .LBB5_4 to .LBB12_4, and .LBB5_3 to .LBB12_1 in instruction info and resource pressure sections.
  • benches/ref_from_suffix_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_suffix_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_suffix_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB13_1 and .LBB5_3 to .LBB13_3.
  • benches/ref_from_suffix_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB13_1 and .LBB5_3 to .LBB13_3 in instruction info and resource pressure sections.
  • benches/ref_from_suffix_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_suffix_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_suffix_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_suffix_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_suffix_static_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB15_2.
  • benches/ref_from_suffix_static_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB15_2 in instruction info and resource pressure sections.
  • benches/ref_from_suffix_with_elems_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_suffix_with_elems_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_suffix_with_elems_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB16_1, .LBB5_5 to .LBB16_5, and .LBB5_4 to .LBB16_4.
  • benches/ref_from_suffix_with_elems_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB16_1, .LBB5_5 to .LBB16_5, and .LBB5_4 to .LBB16_4 in instruction info and resource pressure sections.
  • benches/ref_from_suffix_with_elems_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/ref_from_suffix_with_elems_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/ref_from_suffix_with_elems_dynamic_size.x86-64
    • Updated jump labels from .LBB5_1 to .LBB17_1, .LBB5_5 to .LBB17_5, and .LBB5_4 to .LBB17_4.
  • benches/ref_from_suffix_with_elems_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB17_1, .LBB5_5 to .LBB17_5, and .LBB5_4 to .LBB17_4 in instruction info and resource pressure sections.
  • benches/transmute.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/transmute.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/transmute.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/transmute_ref_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/transmute_ref_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/transmute_ref_dynamic_size.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/transmute_ref_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/transmute_ref_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/transmute_ref_static_size.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/try_read_from_bytes.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_read_from_bytes.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_read_from_bytes.x86-64
    • Updated jump labels from .LBB5_1 to .LBB21_1 and .LBB5_4 to .LBB21_4.
  • benches/try_read_from_bytes.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB21_1 and .LBB5_4 to .LBB21_4 in instruction info and resource pressure sections.
  • benches/try_read_from_prefix.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_read_from_prefix.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_read_from_prefix.x86-64
    • Updated jump labels from .LBB5_2 to .LBB22_2.
  • benches/try_read_from_prefix.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB22_2 in instruction info and resource pressure sections.
  • benches/try_read_from_suffix.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_read_from_suffix.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_read_from_suffix.x86-64
    • Updated jump labels from .LBB5_2 to .LBB23_2.
  • benches/try_read_from_suffix.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB23_2 in instruction info and resource pressure sections.
  • benches/try_ref_from_bytes_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_bytes_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_bytes_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_4 to .LBB24_4 and .LBB5_5 to .LBB24_5.
  • benches/try_ref_from_bytes_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_4 to .LBB24_4 and .LBB5_5 to .LBB24_5 in instruction info and resource pressure sections.
  • benches/try_ref_from_bytes_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_bytes_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_bytes_dynamic_size.x86-64
    • Updated jump labels from .LBB5_4 to .LBB25_4.
  • benches/try_ref_from_bytes_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_4 to .LBB25_4 in instruction info and resource pressure sections.
  • benches/try_ref_from_bytes_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_bytes_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_bytes_static_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB26_2 and .LBB5_3 to .LBB26_3.
  • benches/try_ref_from_bytes_static_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB26_2 and .LBB5_3 to .LBB26_3 in instruction info and resource pressure sections.
  • benches/try_ref_from_bytes_with_elems_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_bytes_with_elems_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_8 to .LBB27_8 and .LBB5_6 to .LBB27_6.
  • benches/try_ref_from_bytes_with_elems_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_8 to .LBB27_8 and .LBB5_6 to .LBB27_6 in instruction info and resource pressure sections.
  • benches/try_ref_from_bytes_with_elems_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_bytes_with_elems_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64
    • Updated jump labels from .LBB5_3 to .LBB28_3 and .LBB5_4 to .LBB28_4.
  • benches/try_ref_from_bytes_with_elems_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_3 to .LBB28_3 and .LBB5_4 to .LBB28_4 in instruction info and resource pressure sections.
  • benches/try_ref_from_prefix_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_prefix_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_prefix_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB29_1 and .LBB5_3 to .LBB29_3.
  • benches/try_ref_from_prefix_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB29_1 and .LBB5_3 to .LBB29_3 in instruction info and resource pressure sections.
  • benches/try_ref_from_prefix_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_prefix_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_prefix_dynamic_size.x86-64
    • Updated jump labels from .LBB5_4 to .LBB30_4 and .LBB5_3 to .LBB30_3.
  • benches/try_ref_from_prefix_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_4 to .LBB30_4 and .LBB5_3 to .LBB30_3 in instruction info and resource pressure sections.
  • benches/try_ref_from_prefix_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_prefix_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_prefix_static_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB31_2 and .LBB5_3 to .LBB31_3.
  • benches/try_ref_from_prefix_static_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB31_2 and .LBB5_3 to .LBB31_3 in instruction info and resource pressure sections.
  • benches/try_ref_from_prefix_with_elems_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_prefix_with_elems_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB32_1, .LBB5_4 to .LBB32_4, and .LBB5_5 to .LBB32_5.
  • benches/try_ref_from_prefix_with_elems_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB32_1, .LBB5_4 to .LBB32_4, and .LBB5_5 to .LBB32_5 in instruction info and resource pressure sections.
  • benches/try_ref_from_prefix_with_elems_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_prefix_with_elems_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64
    • Updated jump labels from .LBB5_1 to .LBB33_1, .LBB5_5 to .LBB33_5, and .LBB5_4 to .LBB33_4.
  • benches/try_ref_from_prefix_with_elems_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB33_1, .LBB5_5 to .LBB33_5, and .LBB5_4 to .LBB33_4 in instruction info and resource pressure sections.
  • benches/try_ref_from_suffix_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_suffix_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_suffix_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB34_1 and .LBB5_3 to .LBB34_3.
  • benches/try_ref_from_suffix_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB34_1 and .LBB5_3 to .LBB34_3 in instruction info and resource pressure sections.
  • benches/try_ref_from_suffix_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_suffix_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_suffix_dynamic_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB35_2.
  • benches/try_ref_from_suffix_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB35_2 in instruction info and resource pressure sections.
  • benches/try_ref_from_suffix_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_suffix_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_suffix_static_size.x86-64
    • Updated jump labels from .LBB5_2 to .LBB36_2.
  • benches/try_ref_from_suffix_static_size.x86-64.mca
    • Updated jump labels from .LBB5_2 to .LBB36_2 in instruction info and resource pressure sections.
  • benches/try_ref_from_suffix_with_elems_dynamic_padding.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_suffix_with_elems_dynamic_padding.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64
    • Updated jump labels from .LBB5_1 to .LBB37_1, .LBB5_4 to .LBB37_4, and .LBB5_5 to .LBB37_5.
  • benches/try_ref_from_suffix_with_elems_dynamic_padding.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB37_1, .LBB5_4 to .LBB37_4, and .LBB5_5 to .LBB37_5 in instruction info and resource pressure sections.
  • benches/try_ref_from_suffix_with_elems_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_ref_from_suffix_with_elems_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64
    • Updated jump labels from .LBB5_1 to .LBB38_1, .LBB5_5 to .LBB38_5, and .LBB5_4 to .LBB38_4.
  • benches/try_ref_from_suffix_with_elems_dynamic_size.x86-64.mca
    • Updated jump labels from .LBB5_1 to .LBB38_1, .LBB5_5 to .LBB38_5, and .LBB5_4 to .LBB38_4 in instruction info and resource pressure sections.
  • benches/try_transmute.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_transmute.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_transmute.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/try_transmute_ref_dynamic_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_transmute_ref_dynamic_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_transmute_ref_dynamic_size.rs
    • Updated zerocopy_derive import to zerocopy.
  • benches/try_transmute_ref_static_size.cortex-m3
    • Added new assembly code for Cortex-M3 target.
  • benches/try_transmute_ref_static_size.generic-rv32
    • Added new assembly code for generic-rv32 target.
  • benches/try_transmute_ref_static_size.rs
    • Updated zerocopy_derive import to zerocopy.
  • tests/codegen.rs
    • Refactored run_codegen_test to accept an IsaConfig struct, enabling testing across multiple ISAs.
    • Introduced IsaConfig struct to define target triple, CPU, and MCA support for each ISA.
    • Modified codegen test to iterate over x86-64, thumbv7m-none-eabi, and riscv32imc-unknown-none-elf targets.
    • Updated cargo asm command to use codegen-benches package and handle target triples and target directories dynamically.
    • Added conditional execution of MCA directive based on IsaConfig.
  • tools/codegen-benches/Cargo.lock
    • Added new Cargo.lock file for the codegen-benches package.
  • tools/codegen-benches/Cargo.toml
    • Added new Cargo.toml file for the codegen-benches package, defining it as a library with zerocopy dependency and panic settings.
  • tools/codegen-benches/build.rs
    • Added a build script to dynamically generate src/lib.rs for codegen-benches by including all .rs files from the benches directory as modules.
  • tools/codegen-benches/src/lib.rs
    • Added new Rust library file, dynamically including benchmark modules from the main benches directory.
  • tools/update-expected-test-output.sh
    • Added rustup target add commands to install thumbv7m-none-eabi and riscv32imc-unknown-none-elf targets.
    • Updated cargo test command for codegen to reflect the new multi-target testing setup.
Ignored Files
  • Ignored by pattern: .github/workflows/** (1)
    • .github/workflows/ci.yml
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Code Review

This pull request extends the codegen tests to track assembly output for thumbv7m-none-eabi and riscv32imc-unknown-none-elf targets, in addition to the existing x86-64 target. This is achieved by introducing a new test harness crate codegen-benches and updating the codegen test logic to iterate over multiple ISA configurations. The changes look good and improve test coverage for different architectures. I have a couple of suggestions to improve the maintainability of the new codegen-benches crate.

@joshlf joshlf force-pushed the Gendq4lo5ioqhx5sfxgkq7iza57vwhm6e branch from d88327b to 5af12b8 Compare March 10, 2026 00:40
@joshlf joshlf changed the title [codegen] Track thumbv7m-none-eabi, riscv32imc-unknown-none-elf codegen [codegen] Track thumbv7m-none-eabi, riscv32imc-unknown-none-elf Mar 10, 2026
@joshlf joshlf changed the base branch from main to Gebjymcx3pko5oy6wx4qr4i6er4i3iodm March 10, 2026 00:40
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codecov-commenter commented Mar 10, 2026

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 91.87%. Comparing base (e62a49e) to head (03a52b6).

Additional details and impacted files
@@                        Coverage Diff                         @@
##           Gebjymcx3pko5oy6wx4qr4i6er4i3iodm    #3103   +/-   ##
==================================================================
  Coverage                              91.87%   91.87%           
==================================================================
  Files                                     20       20           
  Lines                                   6057     6057           
==================================================================
  Hits                                    5565     5565           
  Misses                                   492      492           

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joshlf added 2 commits March 10, 2026 00:59
gherrit-pr-id: Gebjymcx3pko5oy6wx4qr4i6er4i3iodm
gherrit-pr-id: Gendq4lo5ioqhx5sfxgkq7iza57vwhm6e
@joshlf joshlf force-pushed the Gebjymcx3pko5oy6wx4qr4i6er4i3iodm branch from 4993d04 to e62a49e Compare March 10, 2026 00:59
@joshlf joshlf force-pushed the Gendq4lo5ioqhx5sfxgkq7iza57vwhm6e branch from 5af12b8 to 03a52b6 Compare March 10, 2026 00:59
Base automatically changed from Gebjymcx3pko5oy6wx4qr4i6er4i3iodm to main March 10, 2026 03:18
mov rcx, rsi
cmp rsi, 6
jne .LBB5_2
jne .LBB0_2
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Separate from accepting this PR, it looks like we'll need to implement some form of label normalization.

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IIUC this is just because we're changing how compilation works (compiling in a different context with different numbers of basic blocks), which is why this changed. It should still be stable.

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3 participants