Part 1 for School Project on Building a SingleCycle CPU for MIPS (ISA: ChARIS)

Modules Schema

project
|
+---- Modules
|       └─── Control
|       |       |   Control.vhd
|       |
|       └─── DataPath
|               |   Datapath.vhd
|

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
DECSTAGE		DECSTAGE
ALU.vhd		ALU.vhd
ALU_tb.vhd		ALU_tb.vhd
DECSTAGE.vhd		DECSTAGE.vhd
DECSTAGE_tb.vhd		DECSTAGE_tb.vhd
EXSTAGE.vhd		EXSTAGE.vhd
EXSTAGE_tb.vhd		EXSTAGE_tb.vhd
Extender.vhd		Extender.vhd
Extender_tb.vhd		Extender_tb.vhd
Generic_MUX2x1.vhd		Generic_MUX2x1.vhd
Generic_MUX2x1_tb.vhd		Generic_MUX2x1_tb.vhd
MHL312.xise		MHL312.xise
MUX322x1.vhd		MUX322x1.vhd
MUX323x1_tb.vhd		MUX323x1_tb.vhd
MUX52x1.vhd		MUX52x1.vhd
MUX52x1_tb.vhd		MUX52x1_tb.vhd
README.md		README.md
RF.vhd		RF.vhd
RF_tb.vhd		RF_tb.vhd
custom_package.vhd		custom_package.vhd
dec.vhd		dec.vhd
dec_tb.vhd		dec_tb.vhd
mux.vhd		mux.vhd
mux_tb.vhd		mux_tb.vhd
reg.vhd		reg.vhd
reg_tb.vhd		reg_tb.vhd