fix(spi_nand_flash): fix nand flash issue caused by data length unalignment on esp32p4

[RathiSonika]

Change description

When I tested NAND flash on the P4, I found that it was failing at the SPI driver level due to an RX length alignment issue. After reviewing esp_driver_spi, I noticed that SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE is enabled for the ESP32-P4, which requires data length alignment in addition to buffer alignment. I’m adding this fix to handle that requirement.
Adjusted the handling logic to ensure proper alignment, restoring correct flash operation.

[mythbuster5]

spi_nand_program_load what about program direction?

[RathiSonika]

spi_nand_program_load what about program direction?

@mythbuster5 My bad! I hadn’t pushed the latest changes earlier — I’ve done it now. PTAL

[mythbuster5]

LGTM otherwise

[pacucha42]

@RathiSonika please, provide more details in description (how did you find out, related issue reports if any, and other context).
Also rebase your branch as suggested by the bot, and remove 'Dratf' once the PR is ready to merge.

So far, the update looks reasonable

[pacucha42]

Could you also explain how you test the fix? I don't see anything related in your test_app...

[RathiSonika]

Could you also explain how you test the fix? I don't see anything related in your test_app...

If the length is not aligned, the SPI driver will trigger an assertion. This is generally handled by the esp_driver_spi. reference link to check how spi driver handles https://github.com/espressif/esp-idf/blob/master/components/esp_driver_spi/src/gpspi/spi_master.c#L1180

[pacucha42]

Could you also explain how you test the fix? I don't see anything related in your test_app...

If the length is not aligned, the SPI driver will trigger an assertion. This is generally handled by the esp_driver_spi. reference link to check how spi driver handles https://github.com/espressif/esp-idf/blob/master/components/esp_driver_spi/src/gpspi/spi_master.c#L1180

Ok, understand. Thanks

[pacucha42]

Fix approved