Add vector shift/rotate opcode support on IBM Z platform#8120
Add vector shift/rotate opcode support on IBM Z platform#8120ehsankianifar wants to merge 1 commit intoeclipse-omr:masterfrom
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| generateVRRcInstruction(cg, TR::InstOpCode::VN, node, targetReg, sourceReg2, cg->evaluate(maskChild), | ||
| 0, 0, 0); | ||
| cg->decReferenceCount(maskChild); | ||
| isMasked = FALSE; |
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I think it would aid readability if you explained why isMasked is being set to false here.
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I added a comment as you suggested.
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This isn't a comment on this pull request itself, but rather a question about the semantics of the shift and rotate vector operations themselves, and the scalar shift and rotate operations. The OMR how many bits of the second operand are taken into consideration in the operation? Are all thirty-two bits taken into account, which means this would yield a result of zero? Or is the shift amount masked to yield a value in the range 0-15, which would give a shift amount of nine and the result of this operation would be 127? Reading the descriptions of the z/Architecture I think the descriptions of |
Thanks @hzongaro for your comment. As you mentioned, shifting by modulo of the specified value agrees with the Java Vector API (https://docs.oracle.com/en/java/javase/25/docs/api/jdk.incubator.vector/jdk/incubator/vector/VectorOperators.html#LSHL) |
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Introduce support for vector shift and rotate operations in the IBM Z code generator, including masked forms. When a mask is present, the operation is applied only to lanes enabled by the mask. Unmasked lanes preserve their source values to align with vector API semantics. signed-off-by: Ehsan Kiani Far <ehsan.kianifar@gmail.com>
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Introduce support for vector shift and rotate operations in the IBM Z code generator, including masked forms. When a mask is present, the operation is applied only to lanes enabled by the mask. Unmasked lanes preserve their source values to align with vector API semantics.