Implement arithmetic reduction opcodes on IBM Z platform#8094
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ehsankianifar wants to merge 1 commit intoeclipse-omr:masterfrom
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Implement arithmetic reduction opcodes on IBM Z platform#8094ehsankianifar wants to merge 1 commit intoeclipse-omr:masterfrom
ehsankianifar wants to merge 1 commit intoeclipse-omr:masterfrom
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gita-omr
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Feb 4, 2026
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| // Because the operation is performed using scalar FP instructions, the VRF register must overlap with an FPR in the | ||
| // 0–15 range. |
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Thanks. I removed the non ascii char.
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hzongaro
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Feb 6, 2026
| TR::Register *targetReg, TR::Register *scratchReg, TR_IdentityValues identityValue, uint8_t elementSizeMask) | ||
| { | ||
| uint16_t immediateValue = 0; | ||
| uint8_t shiftAmunt = 0; |
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Typo: shiftAmunt should be shiftAmount
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Thanks. Fixed the typo.
Arithmetic reduction opcodes perform lane-wise arithmetic operations (ADD, MUL, MIN, MAX) across all lanes of a vector to produce a single reduced value. The implementation executes the reduction operation on the vector, sign extends the final result, and returns it in a GPR or FPR. The operation may optionally be performed under a mask. When a mask is present, only the masked lanes participate in the reduction. Unmasked lanes are replaced with an identity value so they do not affect the result (e.g., 0 for addition, 1 for multiplication, and appropriate identity values for MIN and MAX). signed-off-by: Ehsan Kiani Far <ehsan.kianifar@gmail.com>
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Arithmetic reduction opcodes perform lane-wise arithmetic operations (ADD, MUL, MIN, MAX) across all lanes of a vector to produce a single reduced value. The implementation executes the reduction operation on the vector, sign extends the final result, and returns it in a GPR or FPR.
The operation may optionally be performed under a mask. When a mask is present, only the masked lanes participate in the reduction. Unmasked lanes are replaced with an identity value so they do not affect the result (e.g., 0 for addition, 1 for multiplication, and appropriate identity values for MIN and MAX).