fix(deps): update riscv

[renovate]

This PR contains the following updates:

Package	Type	Update	Change
riscv	dependencies	minor	0.10.1 → 0.16.0
riscv-rt	dependencies	minor	0.11.0 → 0.17.0

---

Release Notes

rust-embedded/riscv (riscv)

v0.16.0: riscv v0.16.0

Compare Source

A new batch of RISC-V releases is now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details.

riscv-types v0.1.0

This crate substitutes riscv-pac, which is now deprecated

riscv v0.16.0

• Added new CSRs (@​0xllx0 @​KushalMeghani1644)
• New rt and rt-v-trap features to opt-in riscv-rt-related code in riscv::pac_enum macro (@​romancardenas)

riscv-rt v0.17.0

• New no-mhartid and no-xtvec features to support more targets (@​Shatur)
• Fix v-trap core interrupt so RISCV_RT_BASE_ISA must be defined (@​kurtjd)
• Fix stack allocation algorithm for multi-core targets without M extension (@​romancardenas )

v0.15.0: riscv v0.15.0

Compare Source

A new batch of RISC-V releases is now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details.

riscv v0.15.0

• @​rmsyn added proxies to new CSRs.
• @​romancardenas added new methods and associated functions that rely on riscv-pac abstractions for interrupts.
• @​jsgf fixed a bug with the mcause bit mask.

riscv-peripheral v0.4.0

• @​romancardenas added new constant methods to access registers for HART 0.

riscv-rt v0.16.0

This release features numerous exciting changes. The most important are:

• @​bjoernQ added the final necessary changes to allow esp-riscv-rt to run on top of riscv-rt.
• @​romancardenas added linker sections and adapted the boot process to resemble cortex-m-rt and esp-riscv-rt.
• @​janderholm fixed a bug in the linker file. Also, the stack is now split into equal parts based on the number of hearts. In addition, the runtime now avoids some relative jumps to ease the linker placement of code.
• @​jannic and @​Dirbaio merged global_asm macro invocations to avoid potential undefined behavior in future Rust releases.

Other changes

• @​Lumilesto fixed some links in the docs
• @​gibbz00 improved the CI process with spelling checks and improved the docs of riscv-rt

Thank you to all the people who contributed to these releases!

v0.14.0: riscv v0.14.0

Compare Source

A new batch of RISC-V releases are now available at crates.io! Here we enumerate the most important changes, but please read the CHANGELOG.md files for further details

riscv v0.14.0

@​rmsyn added new CSRs. Also, MSRV is now 1.67

riscv-peripheral v0.3.0

This crate experienced a full rework, so the code corresponding to RISC-V peripherals is more natural for PACS generated with svd2rust

riscv-rt v0.15.0

We added the device and memory features to allow PACs to simplify the linking process, similar to cortex-m-rt. If you enable these features, the link.x file will include the device.x and/or memory.x files. In this way, just including link.x in your binary is enough.

The __pre_init symbol has disappeared from riscv-rt by default. If you need it, you must activate the pre_init feature. Also, note that the riscv_rt::pre_init has been deprecated, as it is unsound to execute Rust code before RAM initialization. Instead, use assembly.

We removed weak symbols, as currently stable Rust does not support weak linkage and LTOs. Now, we use _default_* symbols. Once weak linkage is available in stable Rust, we plan to go back to weak symbols. Thanks, @​rslawson !

v0.13.0: riscv 0.13.0

riscv 0.12.0

• CSR writes are now all unsafe. Users can open an RFC to nominate certain CSRs to be safe (#​209)
• All CSR fields are now generated using macros (thanks, @​rmsyn !)
• PACs can now use the RISCV_MTVEC_ALIGN environment variable to set the vector table byte alignment ((thanks, @​ia0 !)

riscv-rt 0.13.0

• Compatibility with RV32E and RV64E!
• Linker script is now more aligned with cortex-m-rt

riscv-target-parser 0.1.0

New utility crate to assist in build scripts of the RISC-V ecosystem. It is useful for determining which extensions are available, the base ISA of the target, etc.

riscv-peripheral 0.2.1 and riscv-semihosting 0.1.3

Update dependencies

v0.12.0: riscv 0.12.0

New features

riscv 0.12.0

• Support for target-dependent external interrupt and exception numbers
• riscv-macros for helping during the definition of custom interrupt and exception sources
• Macros for automating the definition of new CSRs

riscv-pac 0.2.0

• Enumeration of common errors for RISC-V targets at the register level
• All PAC traits now work with usize numbers
• New ExceptionNumber trait for custom exception numbers

riscv-peripheral 0.2.0

• Adapt to new changes in the RISC-V ecosystem

riscv-rt 0.13.0

• Now exceptions rely on the _dispatch_exception function
• Now interrupts rely on the _dispatch_interrupt function
• While the crate provides a default implementation for the previously mentioned functions, you can skip these functions with the new no-exceptions and no-interrupts features. This way, you can adapt riscv-rt to target-specific sources.
• New pre_init_trap to detect early errors during the boot process.
• Vectored interrupts handling is now available under the v-trap feature!
• New core_interrupt, external_interrupt, and exception macros for defining interrupt and exception handlers
• New u-boot feature to execute U-boot binaries.

---

Configuration

📅 Schedule: Branch creation - At any time (no schedule defined), Automerge - At any time (no schedule defined).

🚦 Automerge: Disabled by config. Please merge this manually once you are satisfied.

♻ Rebasing: Whenever PR becomes conflicted, or you tick the rebase/retry checkbox.

👻 Immortal: This PR will be recreated if closed unmerged. Get config help if that's undesired.

---

• If you want to rebase/retry this PR, check this box

---

This PR was generated by Mend Renovate. View the repository job log.