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Merge pull request #294 from cpc/llvm-22 Build and Test #91: Commit 348f92b pushed by pjaaskel
1h 21m 46s main
main
1h 21m 46s
[LLVM 22] Support for the RISC-V-patched LLVM Build and Test #90: Pull request #294 opened by pjaaskel
1h 28m 1s llvm-22
llvm-22
1h 28m 1s
Merge pull request #293 from cpc/llvm-22 Build and Test #89: Commit f4b9893 pushed by pjaaskel
1h 25m 43s main
main
1h 25m 43s
LLVM 22 support without RISC-V Build and Test #88: Pull request #293 synchronize by pjaaskel
1h 28m 34s llvm-22
llvm-22
1h 28m 34s
LLVM 22 support without RISC-V Build and Test #87: Pull request #293 synchronize by pjaaskel
1h 26m 11s llvm-22
llvm-22
1h 26m 11s
LLVM 22 support without RISC-V Build and Test #86: Pull request #293 synchronize by pjaaskel
1h 27m 8s llvm-22
llvm-22
1h 27m 8s
LLVM 22 support without RISC-V Build and Test #85: Pull request #293 synchronize by pjaaskel
1h 19m 3s llvm-22
llvm-22
1h 19m 3s
LLVM 22 support without RISC-V Build and Test #84: Pull request #293 opened by pjaaskel
1h 18m 45s llvm-22
llvm-22
1h 18m 45s
Improving Verilog support in FUGen and adding RFGen Build and Test #83: Pull request #279 synchronize by Joonari
1h 25m 40s fugen-verilog-fixes
fugen-verilog-fixes
1h 25m 40s
Improving Verilog support in FUGen and adding RFGen Build and Test #82: Pull request #279 synchronize by Joonari
1h 24m 45s fugen-verilog-fixes
fugen-verilog-fixes
1h 24m 45s
Improving Verilog support in FUGen and adding RFGen Build and Test #81: Pull request #279 synchronize by Joonari
1m 1s fugen-verilog-fixes
fugen-verilog-fixes
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Improving Verilog support in FUGen and adding RFGen Build and Test #80: Pull request #279 synchronize by Joonari
15m 25s fugen-verilog-fixes
fugen-verilog-fixes
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Improving Verilog support in FUGen and adding RFGen Build and Test #79: Pull request #279 synchronize by Joonari
15m 18s fugen-verilog-fixes
fugen-verilog-fixes
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Improving Verilog support in FUGen and adding RFGen Build and Test #78: Pull request #279 synchronize by Joonari
12m 22s fugen-verilog-fixes
fugen-verilog-fixes
12m 22s
Improving Verilog support in FUGen and adding RFGen Build and Test #77: Pull request #279 synchronize by Joonari
15m 4s fugen-verilog-fixes
fugen-verilog-fixes
15m 4s
Improving Verilog support in FUGen and adding RFGen Build and Test #76: Pull request #279 synchronize by Joonari
4m 15s fugen-verilog-fixes
fugen-verilog-fixes
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Missing datalayout fix Build and Test #75: Commit 94e802b pushed by pjaaskel
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main
1h 30m 7s
Merge pull request #292 from cpc/riscv_opgen_fixes Build and Test #74: Commit e55b512 pushed by pjaaskel
1h 20m 46s main
main
1h 20m 46s
Merge pull request #291 from cpc/ci-step-separation Build and Test #73: Commit 92fe437 pushed by pjaaskel
1h 21m 27s main
main
1h 21m 27s
RISCV opgen fixes Build and Test #72: Pull request #292 opened by karihepola
1h 37m 11s riscv_opgen_fixes
riscv_opgen_fixes
1h 37m 11s
CI: run steps separately Build and Test #71: Pull request #291 synchronize by pjaaskel
4h 3m 30s ci-step-separation
ci-step-separation
4h 3m 30s
CI: run steps separately Build and Test #70: Pull request #291 synchronize by pjaaskel
46m 44s ci-step-separation
ci-step-separation
46m 44s
CI: run steps separately Build and Test #69: Pull request #291 synchronize by pjaaskel
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ci-step-separation
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CI: run steps separately Build and Test #68: Pull request #291 opened by pjaaskel
46m 52s ci-step-separation
ci-step-separation
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Merge pull request #290 from cpc/llvm_21_riscv_fixes Build and Test #67: Commit da22edf pushed by pjaaskel
1h 26m 4s main
main
1h 26m 4s