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1. openCologne openCologne Public

   Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples => https://www.chili-chips.xyz/open-cologne | Also see https:/…

   Verilog 81 7

2. openXC7-TetriSaraj openXC7-TetriSaraj Public

   Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented…

   Verilog 33 3

3. openeye-CamSI openeye-CamSI Public

   A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open …

   SystemVerilog 73 16

4. wireguard-fpga wireguard-fpga Public

   Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…

   Verilog 1.3k 30

5. openCologne-PCIE openCologne-PCIE Public

   The first-ever opensource RTL core for PCIE EndPoint. Without vendor-locked HMs for Data Link, Transaction, Application layers; With standard PIPE interface for vendor SerDes. Portable, unencrypted…

   C++ 51 1

6. openPCIE openPCIE Public

   Peripheral Component Interconnect (PCI) has taken the Express lane long ago, moving to xGbps SerDes... now for the first time in opensource on the Host side too! Our project roots for Root Port in …

   C++ 50 4