Introduction

asysc is an analog system compiler based on the lightweight Computer Algebra System lightcas.

Similar to the VHDL-AMS language, ASysC allows you to create your own components using algebraic descriptions.

For instance, consider the resistor declaration:

NAME.CR(@1,@2,R) := { 
    NAME.U = ACROSS( @1, @2 ); 
    NAME.I = THROUGH( @1, @2 ); 
    NAME.U = R * NAME.I 
};

Additional component definition examples can be found in component.rule file and examples directories.

Requirements

C++ requirement

• g++ or clang
• make

Python requirements

• numpy
• matplotlib

Getting source code

git clone https://github.com/analog-system-compiler/asysc.git
cd asysc
git submodule update --init

Code compilation

make clean
make

Run all tests

make run

Run a specific test

To execute a particular test, type:

cd examples
make
cd examples/<directory>
python3 simulation.py

License

This project is licensed under the GNU General Public License - see the LICENSE file for details.

Examples

Some transient analysis examples

Some AC analysis examples