grt: fix missing via for co-located pins on different layers

[openroad-ci]

Summary

• Fix fillVIA skipping zero-length Steiner edges between co-located pins on different layers by resolving nodes through stackAlias before checking layer info (root cause of RSZ-0074)
• Fix get3DRoute to emit GSegments for zero-length edges that carry via grids (fallback getPlanarRoutes path)
• Fix isCoveringPin to generate via guides for all pin types, not just ports and pad/macro pins
• Add colocated_pins regression test with pins on metal3 and metal4 in the same gcell

Type of Change

• Bug fix

Impact

Create correct vias when colocated pins for different layers.

Verification

• I have verified that the local build succeeds (./etc/Build.sh).
• I have run the relevant tests and they pass.
• My code follows the repository's formatting guidelines.
• I have signed my commits (DCO).

Related Issues

Fixes #9919

[eder-matheus]

@maliberty Secure-CI is running, but I don't expect major changes in our designs.

@povik FYI, I tested with the provided test case and it finishes with no errors.

[gemini-code-assist]

Code Review

This pull request enhances global routing to handle zero-length edges between co-located pins on different layers, preventing the silent dropping of vias. Key modifications include simplifying pin coverage checks in GlobalRouter.cpp, adding logic to process zero-length edges in FastRoute.cpp, and utilizing stackAlias for layer resolution in utility.cpp. Review feedback identifies a logic error in a skip condition in utility.cpp, recommends refactoring duplicated logic in FastRoute.cpp into a helper function, and suggests removing redundant variable assignments.

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"

[github-actions]

clang-tidy review says "All clean, LGTM! 👍"