Creating new Approxy models

New Approxy Models are created within the Approxy/vhdl folder, the VHDL template is located in Approxy/template

Implementing in Go

1. Duplicate Approxy/vhdl/boilerplate.go
2. Rename the struct type from 'Boilerplate' to anything else, modify the methods as well
3. Remove Line 1: //go:build exclude
4. Implement functionality of the functions within Go

To guarantee functionality within Approxy, interfaces are used. Information about Go interfaces can be found elsewhere, but the short explanation is that every Type that implements the correct Methods specified in the Interface, implements this Interface. The Boilerplate code in 'boilerplate.go' implements the VHDLEntityMultiplier Interface.

// VHDLEntityMultiplier is an interface that both implements the functions for VHDLEntity and the Multiplier methods
type VHDLEntityMultiplier interface {
	VHDLEntity
	Multiplier
}

// VHDLEntity describes an interface for testable and synthesizable VHDL structures
type VHDLEntity interface {
	ReturnData() *EntityData
	GenerateVHDL(string)
	GenerateTestData(string)
	GenerateVHDLEntityArray() []VHDLEntity
	String() string //MSB -> LSB
}

// Multiplier describes an interface for generic Multipliers
type Multiplier interface {
	ReturnVal(uint, uint) uint
	Overflow() bool
	MeanAbsoluteError() float64
}

Implementing the VHDL Template

1. Duplicate Approxy/template/boilerplate.vhd
2. Rename file
3. Point Template in func (m *Boilerplate) GenerateVHDL(FolderPath string) to new template
4. Implement Architecture on basis of model within Go
5. Look for examples at other models and templates
6. Go Template Documentation: https://pkg.go.dev/text/template

Default Entities

Multiplier

entity {{.EntityName}} is
generic (word_size: integer:={{.BitSize}}); -- Keep at 2
Port ( 
a : in  STD_LOGIC_VECTOR (word_size-1 downto 0);
b : in  STD_LOGIC_VECTOR (word_size-1 downto 0);
prod: out STD_LOGIC_VECTOR (word_size * 2 - 1 downto 0));
end {{.EntityName}};

MAC

entity {{.EntityName}} is
generic (word_size: integer:={{.BitSize}}; output_size: integer:={{.OutputSize}}); 
Port (
clk : in std_logic;
rst : in std_logic;
A : in  STD_LOGIC_VECTOR (word_size-1 downto 0);
B : in  STD_LOGIC_VECTOR (word_size-1 downto 0);
prod: out STD_LOGIC_VECTOR (output_size-1 downto 0));
end {{.EntityName}};

Scaler

package scaler_pack is
constant scale_int : integer := {{.ScaleN}};
constant word_size : integer := {{.BitSize}};
constant output_size : integer := {{.OutputSize}};
type inputarray is array (0 to scale_int-1) of std_logic_vector(word_size-1 downto 0);
type outputarray is array (0 to scale_int-1) of std_logic_vector(output_size-1 downto 0);
end package scaler_pack;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.scaler_pack.all;

entity {{.EntityName}} is
Port (
{{if .MAC}}
clk : in std_logic;
rst : in std_logic;
{{end}}     
a : in  inputarray;
b : in  inputarray;
prod: out outputarray);
end {{.EntityName}};

NOTE: Any deviation from these standard VHDL entities need careful adjustment. For instance: the test-benches used for verification and Post-P+R analysis most likely will not work due to incompatible IO. A new template for these has to be created as well. Templates used for XSIM start with xsim_ and modification have to be made to Approxy/vivado/XSIM.go