- 👋 Hi, I’m @RKNAGA18
- 👀 I’m interested in python, jave, verilog
- 🌱 I’m currently learning c, embedded c , perl, tcl
- 💞️ I’m looking to collaborate on begginers
- 📫 How to reach me through mail
- 😄 Pronouns: me
- ⚡ Fun fact: information is wealth
INFORMATION IS WEALTH
-
vellore institute of technolgy,chennai
- chennai
- in/naga-arjun-515bb831a
Highlights
- Pro
Popular repositories Loading
-
-
-
Video-Search-and-Upload-Bot-Assignment
Video-Search-and-Upload-Bot-Assignment PublicForked from Tim-Alpha/Video-Search-and-Upload-Bot-Assignment
Python
-
-
Parameterized-Verilog-Generator
Parameterized-Verilog-Generator PublicA Perl-based generator for creating parameterized structural Verilog code for hybrid adders, $N \times N$ multipliers, and N-tap FIR filters.
Perl
-
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.