Computer Architecture - Final Project: CPU Pipeline Simulator

This repository contains the implementation for the Final Project of the Computer Architecture course.
Topic: Simulation of a 5-stage CPU pipeline with hazard detection and forwarding.

Features

• Implements a 5-stage pipeline (IF, ID, EX, MEM, WB)
• Detects and resolves data hazards
• Supports forwarding and stalling
• Provides cycle-by-cycle trace of instruction execution