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Changes to GHDL and Verilator runners
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lines changed

‎batch.py‎

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if url:
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process = subprocess.Popen(
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["python3", "config_generator_core.py", "-n", "-u", url],
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["python3", "config_generator_core.py", "-n","-i", "-u", url],
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stdout=subprocess.PIPE,
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stderr=subprocess.PIPE,
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)

‎config/AUK-V-Aethia.json‎

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{
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"name": "AUK-V-Aethia",
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"folder": "AUK-V-Aethia",
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"sim_files": [],
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"files": [
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"rtl/core/aukv.v",
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"rtl/core/aukv_gpr_regfilie.v"
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],
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"include_dirs": [
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"rtl/core"
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],
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"repository": "https://github.com/veeYceeY/AUK-V-Aethia",
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"top_module": "aukv",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/Anfield.json‎

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{
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"name": "Anfield",
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"folder": "Anfield",
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"sim_files": [],
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"files": [
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"vsrc/Anfield/Anfield.v",
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"vsrc/Anfield/Balotelli/Balotelli.v",
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"vsrc/Anfield/BusMatrix/InstBusMatrix/InstBusMatrix.v",
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"vsrc/Anfield/BusMatrix/DataBusMatix/DataBusMatrix.v",
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"vsrc/Anfield/Peripherals/Memory/Ram.v",
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"vsrc/Anfield/Peripherals/Vga/Vga.v",
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"vsrc/Anfield/Peripherals/Timer/Timer0.v",
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"vsrc/Anfield/Peripherals/Memory/Rom.v",
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"vsrc/Anfield/Balotelli/Pipeline/RegFile.v",
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"vsrc/Anfield/Balotelli/ShareCell/DualPortRam.v",
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"vsrc/Anfield/Balotelli/Pipeline/Ex.v",
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"vsrc/Anfield/Balotelli/Pipeline/Mem2Wb.v",
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"vsrc/Anfield/Balotelli/Pipeline/Id2Ex.v",
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"vsrc/Anfield/Interface/AxiLiteSlaverInterface.v",
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"vsrc/Anfield/Balotelli/Pipeline/Ifu.v",
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"vsrc/Anfield/Balotelli/Pipeline/Mem.v",
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"vsrc/Anfield/Balotelli/Privileged/CrsRegFile.v",
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"vsrc/Anfield/Balotelli/Pipeline/Id.v",
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"vsrc/Anfield/Balotelli/Interface/AxiLiteMasterInterface.v",
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"vsrc/Anfield/Balotelli/Pipeline/Ex2Mem.v",
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"vsrc/Anfield/Balotelli/Pipeline/PrePc.v",
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"vsrc/Anfield/Balotelli/Controler/Ctrl.v",
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"vsrc/Anfield/Balotelli/Controler/Fwu.v",
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"vsrc/Anfield/Balotelli/ALU/Div/Div.v",
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"vsrc/Anfield/Balotelli/Pipeline/If2Id.v",
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"vsrc/Anfield/Balotelli/Pipeline/Pc.v",
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"vsrc/Anfield/Balotelli/Privileged/Clint.v",
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"vsrc/Anfield/Balotelli/ALU/Mul/Mul.v",
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"vsrc/Anfield/Balotelli/Privileged/Plic.v",
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"vsrc/Anfield/Balotelli/Template/RegWithEnHoldData.v",
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"vsrc/Anfield/Balotelli/ALU/Adder/CLA.v",
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"vsrc/Anfield/Balotelli/Template/MuxKeyWithDefault.v",
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"vsrc/Anfield/Balotelli/Template/Reg.v",
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"vsrc/Anfield/Balotelli/ALU/Adder/CasAdder3_2.v",
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"vsrc/Anfield/Balotelli/ALU/Adder/CasAdder4_2.v",
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"vsrc/Anfield/Balotelli/Cache/ICache.v"
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],
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"include_dirs": [
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"vsrc/Anfield/Peripherals/Timer",
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"vsrc/Anfield/BusMatrix/DataBusMatix",
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"vsrc/Anfield/Balotelli/ALU/Adder",
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"vsrc/Anfield/Balotelli/ShareCell",
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"vsrc/Anfield/Peripherals/Memory",
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"vsrc/Anfield/Balotelli/Cache",
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"vsrc/Anfield/Balotelli/Pipeline",
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"vsrc/Anfield/Peripherals/Vga",
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"vsrc/Anfield/Balotelli/Controler",
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"vsrc/Anfield/Interface",
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"vsrc/Anfield/Balotelli/Template",
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"vsrc/Anfield/BusMatrix/InstBusMatrix",
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"vsrc/Anfield/Balotelli/Privileged",
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"vsrc/Anfield/Balotelli/ALU/Div",
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"vsrc/Anfield/Balotelli",
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"vsrc/Anfield/Balotelli/ALU/Mul",
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"vsrc/Anfield/Balotelli/Interface",
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"vsrc/Anfield"
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],
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"repository": "https://github.com/Kaigard/Anfield",
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"top_module": "Anfield",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/Baby-Risco-5.json‎

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{
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"name": "Baby-Risco-5",
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"folder": "Baby-Risco-5",
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"sim_files": [],
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"files": [
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"src/core/core.v",
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"src/core/alu.v",
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"src/core/registers.v",
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"src/core/control_unit.v",
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"src/core/immediate_generator.v",
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"src/core/alu_control.v"
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],
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"include_dirs": [
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"src/core"
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],
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"repository": "https://github.com/JN513/Baby-Risco-5",
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"top_module": "Core",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/F03x.json‎

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{
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"name": "F03x",
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"folder": "F03x",
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"sim_files": [],
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"files": [
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"klessydra-f0-3th/PKG_RiscV_Klessydra_thread_parameters.vhd",
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"klessydra-f0-3th/PKG_RiscV_Klessydra.vhd",
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"klessydra-f0-3th/STR-Klessydra_top.vhd",
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"klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd",
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"klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd",
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"klessydra-f0-3th/RTL-Debug_Unit.vhd",
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"klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd",
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"klessydra-f0-3th/TMR_REG_PKG.vhd",
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"klessydra-f0-3th/CMP-TMR_REG.vhd"
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],
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"include_dirs": [],
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"repository": "https://github.com/klessydra/F03x",
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"top_module": "klessydra_f0_3th_core",
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"extra_flags": [],
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"language_version": "08",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/Grande-Risco-5.json‎

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{
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"name": "Grande-Risco-5",
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"folder": "Grande-Risco-5",
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"sim_files": [],
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"files": [
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"rtl/core/grande_risco5_types.sv",
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"rtl/core/core.sv",
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"rtl/core/csr_unit.sv",
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"rtl/core/ir_decomp.sv",
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"rtl/core/branch_prediction.sv",
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"rtl/core/mux.sv",
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"rtl/core/invalid_ir_check.sv",
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"rtl/core/alu.sv",
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"rtl/core/registers.sv",
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"rtl/core/forwarding_unit.sv",
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"rtl/core/immediate_generator.sv",
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"rtl/core/alu_control.sv",
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"rtl/core/mdu.sv"
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],
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"include_dirs": [
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"rtl/core"
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],
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"repository": "https://github.com/JN513/Grande-Risco-5",
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"top_module": "Core",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/Hazard3.json‎

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{
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"name": "Hazard3",
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"folder": "Hazard3",
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"sim_files": [],
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"files": [
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"hdl/hazard3_core.v",
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"hdl/arith/hazard3_alu.v",
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"hdl/arith/hazard3_branchcmp.v",
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"hdl/arith/hazard3_muldiv_seq.v"
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],
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"include_dirs": [
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"hdl/arith",
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"hdl"
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],
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"repository": "https://github.com/Wren6991/Hazard3",
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"top_module": "hazard3_core",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/Pequeno-Risco-5.json‎

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{
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"name": "Pequeno-Risco-5",
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"folder": "Pequeno-Risco-5",
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"sim_files": [],
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"files": [
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"src/core.v",
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"src/data_memory.v",
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"src/alu_control.v",
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"src/immediate_generator.v",
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"src/mux.v",
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"src/control_unit.v",
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"src/alu.v",
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"src/registers.v",
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"src/instruction_memory.v",
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"src/pc.v"
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],
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"include_dirs": [
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"src"
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],
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"repository": "https://github.com/JN513/Pequeno-Risco-5",
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"top_module": "Core",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/RISC-V.json‎

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{
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"name": "RISC-V",
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"folder": "RISC-V",
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"sim_files": [],
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"files": [
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"core/core.v",
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"core/muldiv/MULDIV_top.v",
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"core/muldiv/MUL_DIV_out.v"
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],
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"include_dirs": [
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"core",
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"core/muldiv"
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],
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"repository": "https://github.com/yavuz650/RISC-V",
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"top_module": "core",
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"extra_flags": [],
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"language_version": "1800-2017",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

‎config/RISCV-EC.json‎

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{
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"name": "RISCV-EC",
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"folder": "RISCV-EC",
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"sim_files": [],
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"files": [
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"rtl/sum.vhd"
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],
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"include_dirs": [],
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"repository": "https://github.com/guianmon99/RISCV-EC.git",
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"top_module": "sum",
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"extra_flags": [],
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"language_version": "08",
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"march": "rv32i",
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"two_memory": false,
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"is_simulable": true
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}

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