Changes to verilator runner

Author: gabcro

config/AUK-V-Aethia.json

@@ -0,0 +1,58 @@
+{
+    "name": "Cores-VeeR-EH1",
+    "folder": "Cores-VeeR-EH1",
+    "sim_files": [],
+    "files": [
+        "design/dmi/dmi_jtag_to_core_sync.v",
+        "design/dmi/dmi_wrapper.v",
+        "design/dma_ctrl.sv",
+        "design/mem.sv",
+        "design/pic_ctrl.sv",
+        "design/veer.sv",
+        "design/veer_wrapper.sv",
+        "design/dbg/dbg.sv",
+        "design/dec/dec.sv",
+        "design/dec/dec_decode_ctl.sv",
+        "design/dec/dec_gpr_ctl.sv",
+        "design/dec/dec_ib_ctl.sv",
+        "design/dec/dec_tlu_ctl.sv",
+        "design/dec/dec_trigger.sv",
+        "design/dmi/rvjtag_tap.sv",
+        "design/exu/exu.sv",
+        "design/exu/exu_alu_ctl.sv",
+        "design/exu/exu_div_ctl.sv",
+        "design/exu/exu_mul_ctl.sv",
+        "design/ifu/ifu.sv",
+        "design/ifu/ifu_aln_ctl.sv",
+        "design/ifu/ifu_bp_ctl.sv",
+        "design/ifu/ifu_compress_ctl.sv",
+        "design/ifu/ifu_ic_mem.sv",
+        "design/ifu/ifu_iccm_mem.sv",
+        "design/ifu/ifu_ifc_ctl.sv",
+        "design/ifu/ifu_mem_ctl.sv",
+        "design/include/veer_types.sv",
+        "design/lib/ahb_to_axi4.sv",
+        "design/lib/axi4_to_ahb.sv",
+        "design/lib/beh_lib.sv",
+        "design/lib/mem_lib.sv",
+        "design/lib/svci_to_axi4.sv",
+        "design/lsu/lsu.sv",
+        "design/lsu/lsu_addrcheck.sv",
+        "design/lsu/lsu_bus_buffer.sv",
+        "design/lsu/lsu_bus_intf.sv",
+        "design/lsu/lsu_clkdomain.sv",
+        "design/lsu/lsu_dccm_ctl.sv",
+        "design/lsu/lsu_dccm_mem.sv",
+        "design/lsu/lsu_ecc.sv",
+        "design/lsu/lsu_lsc_ctl.sv",
+        "design/lsu/lsu_trigger.sv"
+    ],
+    "include_dirs": [],
+    "repository": "https://github.com/chipsalliance/Cores-VeeR-EH1",
+    "top_module": "",
+    "extra_flags": [],
+    "language_version": "1800-2017",
+    "march": "rv32i",
+    "two_memory": false,
+    "is_simulable": false
+}