Corrigindo ahb to wishbone

Author: JN513

config/F03x.json

@@ -7,11 +7,11 @@
         "klessydra-f0-3th/PKG_RiscV_Klessydra.vhd",
         "klessydra-f0-3th/TMR_REG_PKG.vhd",
         "klessydra-f0-3th/CMP-TMR_REG.vhd",
-        "klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd",
-        "klessydra-f0-3th/RTL-Debug_Unit.vhd",
         "klessydra-f0-3th/RTL-Processing_Pipeline_TMR.vhd",
         "klessydra-f0-3th/RTL-Program_Counter_unit_TMR.vhd",
-        "klessydra-f0-3th/STR-Klessydra_top.vhd"
+        "klessydra-f0-3th/STR-Klessydra_top.vhd",
+        "klessydra-f0-3th/RTL-CSR_Unit_TMR.vhd",
+        "klessydra-f0-3th/RTL-Debug_Unit.vhd"
     ],
     "include_dirs": [],
     "repository": "https://github.com/klessydra/F03x",

internal/ahblite_to_wishbone.sv

@@ -37,7 +37,8 @@ module ahb_to_wishbone #(
     logic [2:0] beat_size;
 
     // AHB access condition
-    logic ahb_access = (HTRANS[1] || HWRITE) && HREADY;
+    logic ahb_access;
+    assign ahb_access = (HTRANS[1] || HWRITE) && HREADY;
     logic ready;
 
     // Response and read data
@@ -47,7 +48,8 @@ module ahb_to_wishbone #(
     assign wb_dat_w  = HWDATA;
 
     // Burst type check
-    logic is_burst = |HBURST; // Not SINGLE
+    logic is_burst
+    assign is_burst = |HBURST; // Not SINGLE
 
     always_ff @(posedge HCLK or negedge HRESETn) begin
         if (!HRESETn) begin