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JN513JN513
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Corrigindo erro no wr_strb da memoria de dados
Corrigindo data_mem_wr_strb para data_mem_wstrb. Movendo conversores nos arquivos de config do processor-ci-controller para o processor_ci
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99 files changed

+153
-5457
lines changed

‎build_scripts/colorlight_i9.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
11
yosys read_systemverilog -defer /eda/processor-ci-controller/modules/uart.sv
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yosys read_systemverilog -defer /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
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yosys read_systemverilog -defer /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
4-
yosys read_systemverilog -defer /eda/processor-ci-controller/rtl/ahblite_to_wishbone.svls
5-
yosys read_systemverilog -defer /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv
6-
yosys read_systemverilog -defer /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv
4+
yosys read_systemverilog -defer /eda/processor_ci/internal/ahblite_to_wishbone.svls
5+
yosys read_systemverilog -defer /eda/processor_ci/internal/axi4_to_wishbone.sv
6+
yosys read_systemverilog -defer /eda/processor_ci/internal/axi4lite_to_wishbone.sv
77
yosys read_systemverilog -defer /eda/processor-ci-controller/rtl/fifo.sv
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yosys read_systemverilog -defer /eda/processor-ci-controller/rtl/reset.sv
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yosys read_systemverilog -defer /eda/processor-ci-controller/rtl/clk_divider.sv

‎build_scripts/digilent_arty_a7_100t.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@ read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
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#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
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#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;
77

8-
read_verilog -sv /eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv
9-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv
10-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv
8+
read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
9+
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
10+
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
1111
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
1212
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
1313
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv

‎build_scripts/digilent_nexys4_ddr.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@ read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
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#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
66
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;
77

8-
read_verilog -sv /eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv
9-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv
10-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv
8+
read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
9+
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
10+
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
1111
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
1212
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
1313
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv

‎build_scripts/gowin_tangnano_20k.tcl‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,9 @@ add_file /eda/processor-ci-controller/rtl/interpreter.sv
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add_file /eda/processor-ci-controller/rtl/controller.sv
1515
add_file /eda/processor-ci-controller/rtl/timer.sv
1616
add_file /eda/processor_ci/internal/fpga_top.sv
17+
add_file /eda/processor_ci/internal/ahblite_to_wishbone.sv
18+
add_file /eda/processor_ci/internal/axi4_to_wishbone.sv
19+
add_file /eda/processor_ci/internal/axi4lite_to_wishbone.sv
1720

1821
set_option -top_module fpga_top
1922

‎build_scripts/opensdrlab_kintex7.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@ read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
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#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
66
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;
77

8-
read_verilog -sv /eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv
9-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv
10-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv
8+
read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
9+
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
10+
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
1111
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
1212
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
1313
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv

‎build_scripts/xilinx_vc709.tcl‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -5,9 +5,9 @@ read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
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#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
66
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;
77

8-
read_verilog -sv /eda/processor-ci-controller/rtl/ahblite_to_wishbone.sv
9-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4_to_wishbone.sv
10-
read_verilog -sv /eda/processor-ci-controller/rtl/axi4lite_to_wishbone.sv
8+
read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
9+
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
10+
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
1111
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
1212
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
1313
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv

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