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Adicionando wstrb
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‎rtl/AUK-V-Aethia.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ module processorci_top (
3030
output logic core_stb, // Indica uma solicitação ativa
3131
output logic core_we, // 1 = Write, 0 = Read
3232

33+
output logic [3:0] core_wstrb,
3334
output logic [31:0] core_addr, // Endereço
3435
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3536
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -41,6 +42,7 @@ module processorci_top (
4142
output logic data_mem_cyc,
4243
output logic data_mem_stb,
4344
output logic data_mem_we,
45+
output logic [3:0] data_mem_wr_strb,
4446
output logic [31:0] data_mem_addr,
4547
output logic [31:0] data_mem_data_out,
4648
input logic [31:0] data_mem_data_in,
@@ -59,6 +61,7 @@ assign rst_core = ~rst_n;
5961
logic core_cyc;
6062
logic core_stb;
6163
logic core_we;
64+
logic [3:0] core_wstrb;
6265
logic [31:0] core_addr;
6366
logic [31:0] core_data_out;
6467
logic [31:0] core_data_in;
@@ -68,6 +71,7 @@ logic core_ack;
6871
logic data_mem_cyc;
6972
logic data_mem_stb;
7073
logic data_mem_we;
74+
logic [3:0] data_mem_wstrb;
7175
logic [31:0] data_mem_addr;
7276
logic [31:0] data_mem_data_out;
7377
logic [31:0] data_mem_data_in;

‎rtl/Anfield.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ module processorci_top (
2828
output logic core_stb, // Indica uma solicitação ativa
2929
output logic core_we, // 1 = Write, 0 = Read
3030

31+
output logic [3:0] core_wstrb,
3132
output logic [31:0] core_addr, // Endereço
3233
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3334
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -39,6 +40,7 @@ module processorci_top (
3940
output logic data_mem_cyc,
4041
output logic data_mem_stb,
4142
output logic data_mem_we,
43+
output logic [3:0] data_mem_wr_strb,
4244
output logic [31:0] data_mem_addr,
4345
output logic [31:0] data_mem_data_out,
4446
input logic [31:0] data_mem_data_in,
@@ -57,6 +59,7 @@ assign rst_core = ~rst_n;
5759
logic core_cyc;
5860
logic core_stb;
5961
logic core_we;
62+
logic [3:0] core_wstrb;
6063
logic [31:0] core_addr;
6164
logic [31:0] core_data_out;
6265
logic [31:0] core_data_in;
@@ -66,6 +69,7 @@ logic core_ack;
6669
logic data_mem_cyc;
6770
logic data_mem_stb;
6871
logic data_mem_we;
72+
logic [3:0] data_mem_wstrb;
6973
logic [31:0] data_mem_addr;
7074
logic [31:0] data_mem_data_out;
7175
logic [31:0] data_mem_data_in;

‎rtl/Baby-Risco-5.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ module processorci_top (
2828
output logic core_stb, // Indica uma solicitação ativa
2929
output logic core_we, // 1 = Write, 0 = Read
3030

31+
output logic [3:0] core_wstrb,
3132
output logic [31:0] core_addr, // Endereço
3233
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3334
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -39,6 +40,7 @@ module processorci_top (
3940
output logic data_mem_cyc,
4041
output logic data_mem_stb,
4142
output logic data_mem_we,
43+
output logic [3:0] data_mem_wr_strb,
4244
output logic [31:0] data_mem_addr,
4345
output logic [31:0] data_mem_data_out,
4446
input logic [31:0] data_mem_data_in,
@@ -57,6 +59,7 @@ assign rst_core = ~rst_n;
5759
logic core_cyc;
5860
logic core_stb;
5961
logic core_we;
62+
logic [3:0] core_wstrb;
6063
logic [31:0] core_addr;
6164
logic [31:0] core_data_out;
6265
logic [31:0] core_data_in;
@@ -66,6 +69,7 @@ logic core_ack;
6669
logic data_mem_cyc;
6770
logic data_mem_stb;
6871
logic data_mem_we;
72+
logic [3:0] data_mem_wstrb;
6973
logic [31:0] data_mem_addr;
7074
logic [31:0] data_mem_data_out;
7175
logic [31:0] data_mem_data_in;

‎rtl/Cores-SweRV-EH2.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module processorci_top (
3131
output logic core_stb, // Indica uma solicitação ativa
3232
output logic core_we, // 1 = Write, 0 = Read
3333

34+
output logic [3:0] core_wstrb,
3435
output logic [31:0] core_addr, // Endereço
3536
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3637
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -42,6 +43,7 @@ module processorci_top (
4243
output logic data_mem_cyc,
4344
output logic data_mem_stb,
4445
output logic data_mem_we,
46+
output logic [3:0] data_mem_wr_strb,
4547
output logic [31:0] data_mem_addr,
4648
output logic [31:0] data_mem_data_out,
4749
input logic [31:0] data_mem_data_in,
@@ -60,6 +62,7 @@ assign rst_core = ~rst_n;
6062
logic core_cyc;
6163
logic core_stb;
6264
logic core_we;
65+
logic [3:0] core_wstrb;
6366
logic [31:0] core_addr;
6467
logic [31:0] core_data_out;
6568
logic [31:0] core_data_in;
@@ -69,6 +72,7 @@ logic core_ack;
6972
logic data_mem_cyc;
7073
logic data_mem_stb;
7174
logic data_mem_we;
75+
logic [3:0] data_mem_wstrb;
7276
logic [31:0] data_mem_addr;
7377
logic [31:0] data_mem_data_out;
7478
logic [31:0] data_mem_data_in;

‎rtl/Cores-SweRV-EL2.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module processorci_top (
3131
output logic core_stb, // Indica uma solicitação ativa
3232
output logic core_we, // 1 = Write, 0 = Read
3333

34+
output logic [3:0] core_wstrb,
3435
output logic [31:0] core_addr, // Endereço
3536
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3637
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -42,6 +43,7 @@ module processorci_top (
4243
output logic data_mem_cyc,
4344
output logic data_mem_stb,
4445
output logic data_mem_we,
46+
output logic [3:0] data_mem_wr_strb,
4547
output logic [31:0] data_mem_addr,
4648
output logic [31:0] data_mem_data_out,
4749
input logic [31:0] data_mem_data_in,
@@ -60,6 +62,7 @@ assign rst_core = ~rst_n;
6062
logic core_cyc;
6163
logic core_stb;
6264
logic core_we;
65+
logic [3:0] core_wstrb;
6366
logic [31:0] core_addr;
6467
logic [31:0] core_data_out;
6568
logic [31:0] core_data_in;
@@ -69,6 +72,7 @@ logic core_ack;
6972
logic data_mem_cyc;
7073
logic data_mem_stb;
7174
logic data_mem_we;
75+
logic [3:0] data_mem_wstrb;
7276
logic [31:0] data_mem_addr;
7377
logic [31:0] data_mem_data_out;
7478
logic [31:0] data_mem_data_in;

‎rtl/Cores-SweRV.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module processorci_top (
3131
output logic core_stb, // Indica uma solicitação ativa
3232
output logic core_we, // 1 = Write, 0 = Read
3333

34+
output logic [3:0] core_wstrb,
3435
output logic [31:0] core_addr, // Endereço
3536
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3637
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -42,6 +43,7 @@ module processorci_top (
4243
output logic data_mem_cyc,
4344
output logic data_mem_stb,
4445
output logic data_mem_we,
46+
output logic [3:0] data_mem_wr_strb,
4547
output logic [31:0] data_mem_addr,
4648
output logic [31:0] data_mem_data_out,
4749
input logic [31:0] data_mem_data_in,
@@ -60,6 +62,7 @@ assign rst_core = ~rst_n;
6062
logic core_cyc;
6163
logic core_stb;
6264
logic core_we;
65+
logic [3:0] core_wstrb;
6366
logic [31:0] core_addr;
6467
logic [31:0] core_data_out;
6568
logic [31:0] core_data_in;
@@ -69,6 +72,7 @@ logic core_ack;
6972
logic data_mem_cyc;
7073
logic data_mem_stb;
7174
logic data_mem_we;
75+
logic [3:0] data_mem_wstrb;
7276
logic [31:0] data_mem_addr;
7377
logic [31:0] data_mem_data_out;
7478
logic [31:0] data_mem_data_in;

‎rtl/Cores-VeeR-EH1.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module processorci_top (
3131
output logic core_stb, // Indica uma solicitação ativa
3232
output logic core_we, // 1 = Write, 0 = Read
3333

34+
output logic [3:0] core_wstrb,
3435
output logic [31:0] core_addr, // Endereço
3536
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3637
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -42,6 +43,7 @@ module processorci_top (
4243
output logic data_mem_cyc,
4344
output logic data_mem_stb,
4445
output logic data_mem_we,
46+
output logic [3:0] data_mem_wr_strb,
4547
output logic [31:0] data_mem_addr,
4648
output logic [31:0] data_mem_data_out,
4749
input logic [31:0] data_mem_data_in,
@@ -60,6 +62,7 @@ assign rst_core = ~rst_n;
6062
logic core_cyc;
6163
logic core_stb;
6264
logic core_we;
65+
logic [3:0] core_wstrb;
6366
logic [31:0] core_addr;
6467
logic [31:0] core_data_out;
6568
logic [31:0] core_data_in;
@@ -69,6 +72,7 @@ logic core_ack;
6972
logic data_mem_cyc;
7073
logic data_mem_stb;
7174
logic data_mem_we;
75+
logic [3:0] data_mem_wstrb;
7276
logic [31:0] data_mem_addr;
7377
logic [31:0] data_mem_data_out;
7478
logic [31:0] data_mem_data_in;

‎rtl/Cores-VeeR-EH2.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module processorci_top (
3131
output logic core_stb, // Indica uma solicitação ativa
3232
output logic core_we, // 1 = Write, 0 = Read
3333

34+
output logic [3:0] core_wstrb,
3435
output logic [31:0] core_addr, // Endereço
3536
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3637
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -42,6 +43,7 @@ module processorci_top (
4243
output logic data_mem_cyc,
4344
output logic data_mem_stb,
4445
output logic data_mem_we,
46+
output logic [3:0] data_mem_wr_strb,
4547
output logic [31:0] data_mem_addr,
4648
output logic [31:0] data_mem_data_out,
4749
input logic [31:0] data_mem_data_in,
@@ -60,6 +62,7 @@ assign rst_core = ~rst_n;
6062
logic core_cyc;
6163
logic core_stb;
6264
logic core_we;
65+
logic [3:0] core_wstrb;
6366
logic [31:0] core_addr;
6467
logic [31:0] core_data_out;
6568
logic [31:0] core_data_in;
@@ -69,6 +72,7 @@ logic core_ack;
6972
logic data_mem_cyc;
7073
logic data_mem_stb;
7174
logic data_mem_we;
75+
logic [3:0] data_mem_wstrb;
7276
logic [31:0] data_mem_addr;
7377
logic [31:0] data_mem_data_out;
7478
logic [31:0] data_mem_data_in;

‎rtl/Cores-VeeR-EL2.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ module processorci_top (
3131
output logic core_stb, // Indica uma solicitação ativa
3232
output logic core_we, // 1 = Write, 0 = Read
3333

34+
output logic [3:0] core_wstrb,
3435
output logic [31:0] core_addr, // Endereço
3536
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3637
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -42,6 +43,7 @@ module processorci_top (
4243
output logic data_mem_cyc,
4344
output logic data_mem_stb,
4445
output logic data_mem_we,
46+
output logic [3:0] data_mem_wr_strb,
4547
output logic [31:0] data_mem_addr,
4648
output logic [31:0] data_mem_data_out,
4749
input logic [31:0] data_mem_data_in,
@@ -60,6 +62,7 @@ assign rst_core = ~rst_n;
6062
logic core_cyc;
6163
logic core_stb;
6264
logic core_we;
65+
logic [3:0] core_wstrb;
6366
logic [31:0] core_addr;
6467
logic [31:0] core_data_out;
6568
logic [31:0] core_data_in;
@@ -69,6 +72,7 @@ logic core_ack;
6972
logic data_mem_cyc;
7073
logic data_mem_stb;
7174
logic data_mem_we;
75+
logic [3:0] data_mem_wstrb;
7276
logic [31:0] data_mem_addr;
7377
logic [31:0] data_mem_data_out;
7478
logic [31:0] data_mem_data_in;

‎rtl/F03x.sv‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,7 @@ module processorci_top (
3030
output logic core_stb, // Indica uma solicitação ativa
3131
output logic core_we, // 1 = Write, 0 = Read
3232

33+
output logic [3:0] core_wstrb,
3334
output logic [31:0] core_addr, // Endereço
3435
output logic [31:0] core_data_out, // Dados de entrada (para escrita)
3536
input logic [31:0] core_data_in, // Dados de saída (para leitura)
@@ -41,6 +42,7 @@ module processorci_top (
4142
output logic data_mem_cyc,
4243
output logic data_mem_stb,
4344
output logic data_mem_we,
45+
output logic [3:0] data_mem_wr_strb,
4446
output logic [31:0] data_mem_addr,
4547
output logic [31:0] data_mem_data_out,
4648
input logic [31:0] data_mem_data_in,
@@ -59,6 +61,7 @@ assign rst_core = ~rst_n;
5961
logic core_cyc;
6062
logic core_stb;
6163
logic core_we;
64+
logic [3:0] core_wstrb;
6265
logic [31:0] core_addr;
6366
logic [31:0] core_data_out;
6467
logic [31:0] core_data_in;
@@ -68,6 +71,7 @@ logic core_ack;
6871
logic data_mem_cyc;
6972
logic data_mem_stb;
7073
logic data_mem_we;
74+
logic [3:0] data_mem_wstrb;
7175
logic [31:0] data_mem_addr;
7276
logic [31:0] data_mem_data_out;
7377
logic [31:0] data_mem_data_in;

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