Reestruturando projeto

.github/workflows/clk_divider.yml

@@ -0,0 +1,29 @@
+name: ClkDivider Test
+
+on: [push, pull_request]
+
+jobs:
+  test:
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout do código
+        uses: actions/checkout@v4
+
+      - name: Instalar Icarus Verilog (iverilog)
+        run: sudo apt update && sudo apt install -y iverilog
+
+      - name: Criar diretório de build
+        run: mkdir -p build
+
+      - name: Compilar o testbench
+        run: iverilog -o build/ClkDivider_tb -s ClkDivider_tb -g2005-sv -Irtl/core testbenchs/clk_divider_tb.sv rtl/clk_divider.sv
+
+      - name: Executar o testbench
+        run: vvp build/ClkDivider_tb
+
+      - name: Salvar VCD como artefato
+        uses: actions/upload-artifact@v4
+        with:
+          name: fifo_waveform
+          path: build/ClkDivider_tb.vcd

.github/workflows/fifo.yml

@@ -0,0 +1,29 @@
+name: FIFO Test
+
+on: [push, pull_request]
+
+jobs:
+  test:
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout do código
+        uses: actions/checkout@v4
+
+      - name: Instalar Icarus Verilog (iverilog)
+        run: sudo apt update && sudo apt install -y iverilog
+
+      - name: Criar diretório de build
+        run: mkdir -p build
+
+      - name: Compilar o testbench
+        run: iverilog -o build/fifo_tb -s fifo_tb -g2005-sv -Irtl/core testbenchs/fifo_tb.sv rtl/fifo.sv
+
+      - name: Executar o testbench
+        run: vvp build/fifo_tb
+
+      - name: Salvar VCD como artefato
+        uses: actions/upload-artifact@v4
+        with:
+          name: fifo_waveform
+          path: build/fifo_tb.vcd

.gitignore

@@ -19,3 +19,6 @@ webtalk*.log
 webtalk*.jou
 fpga/digilent_arty/usage_statistics_webtalk.xml
 fpga/digilent_arty/usage_statistics_webtalk.html
+fpga/nexys4_ddr/clockInfo.txt
+fpga/nexys4_ddr/usage_statistics_webtalk.html
+fpga/nexys4_ddr/usage_statistics_webtalk.xml

.gitmodules

@@ -3,7 +3,4 @@
 	url = https://github.com/Unicamp-Odhin/SPI-Slave
 [submodule "modules/UART"]
 	path = modules/UART
-	url = https://github.com/ben-marshall/uart
-[submodule "modules/Risco-5"]
-	path = modules/Risco-5
-	url = https://github.com/JN513/Risco-5
+	url = https://github.com/ben-marshall/uart

examples/Grande-Risco-5.sv

@@ -0,0 +1,103 @@
+module top (
+    input  logic clk,
+    input  logic CPU_RESETN,
+
+    input  logic rx,
+    output logic tx,
+
+    input  logic mosi,
+    output logic miso,
+    input  logic sck,
+    input  logic cs
+);
+
+logic clk_o;
+logic clk_core, rst_core;
+
+// Fios do barramento entre Controller e Processor
+logic core_cyc;
+logic core_stb;
+logic core_we;
+logic [31:0] core_addr;
+logic [31:0] core_data_out;
+logic [31:0] core_data_in;
+logic        core_ack;
+
+Controller #(
+    .CLK_FREQ           (50000000),
+    .BIT_RATE           (BIT_RATE),
+    .PAYLOAD_BITS       (8),
+    .BUFFER_SIZE        (8),
+    .PULSE_CONTROL_BITS (32),
+    .BUS_WIDTH          (32),
+    .WORD_SIZE_BY       (4),
+    .ID                 (32'h7700006A),
+    .RESET_CLK_CYCLES   (20),
+    .MEMORY_FILE        (""),
+    .MEMORY_SIZE        (4096)
+) u_Controller (
+    .clk                (clk),
+    .rst_n              (CPU_RESETN),
+
+    // SPI signals
+    .sck_i              (sck),
+    .cs_i               (cs),
+    .mosi_i             (mosi),
+    .miso_o             (miso),
+
+    // SPI callback signals
+    .rw_i               (),
+    .intr_o             (),
+
+    // UART signals
+    .rx                 (rx),
+    .tx                 (tx),
+
+    // Clock, reset, and bus signals
+    .clk_core_o         (clk_core),
+    .rst_core_o         (rst_core),
+
+    // Barramento padrão (não AXI4-Lite)
+    .core_cyc_i         (core_cyc),
+    .core_stb_i         (core_stb),
+    .core_we_i          (core_we),
+    .core_addr_i        (core_addr),
+    .core_data_i        (core_data_out),
+    .core_data_o        (core_data_in),
+    .core_ack_o         (core_ack)
+);
+
+Grande_Risco5 #(
+    .BOOT_ADDRESS           (32'h00000000),
+    .I_CACHE_SIZE           (256),
+    .D_CACHE_SIZE           (256),
+    .DATA_WIDTH             (32),
+    .ADDR_WIDTH             (32),
+    .BRANCH_PREDICTION_SIZE (128)
+) Processor (
+    .clk    (clk_core),
+    .rst_n  (~rst_core),
+    .halt   (1'b0),
+
+    .cyc_o  (core_cyc),
+    .stb_o  (core_stb),
+    .we_o   (core_we),
+
+    .addr_o (core_addr),
+    .data_o (core_data_out),
+
+    .ack_i  (core_ack),
+    .data_i (core_data_in),
+
+    .interruption (1'b0)
+);
+
+always_ff @(posedge clk) begin : CLOCK_DIVIDER
+    if (!CPU_RESETN) begin
+        clk_o <= 1'b0;
+    end else begin
+        clk_o <= ~clk_o;
+    end
+end
+
+endmodule

fpga/nexys4_ddr/.gitignore

@@ -3,4 +3,5 @@ digilent_arty.hw/
 digilent_arty.ip_user_files/
 .Xil/
 report/
-vivado_*.backup.*
+vivado_*.backup.*
+reports

fpga/nexys4_ddr/Makefile

@@ -1,15 +1,27 @@
+ifndef VIVADO_PATH
+	VIVADO=vivado
+else
+	VIVADO=$(VIVADO_PATH)/vivado
+endif
+
 all: ./build/out.bit
 
 ./build/out.bit: buildFolder
-	vivado -mode batch -nolog -nojournal -source run.tcl
+	$(VIVADO) -mode batch -nolog -nojournal -source run.tcl
 buildFolder:
 	mkdir -p build
+	mkdir -p reports
 
 clean:
 	rm -rf build
-	rm clockInfo.txt
+	rm -rf clockInfo.txt
+	rm -rf .Xil
+	rm -rf reports
 
-flash:
+load:
 	openFPGALoader -b nexys_a7_100 ./build/out.bit
 
-run_all: ./build/out.bit flash
+flash:
+	openFPGALoader -b nexys_a7_100 -f ./build/out.bit
+
+run_all: ./build/out.bit load

fpga/nexys4_ddr/main.sv

@@ -0,0 +1,99 @@
+module top (
+    input  logic clk,
+    input  logic CPU_RESETN,
+
+    input  logic rx,
+    output logic tx,
+
+    output logic [15:0]LED,
+
+    input  logic mosi,
+    output logic miso,
+    input  logic sck,
+    input  logic cs,
+
+    input  logic [15:0] SW,
+
+    output logic [3:0] VGA_R,
+    output logic [3:0] VGA_G,
+    output logic [3:0] VGA_B,
+    output logic VGA_HS,
+    output logic VGA_VS,
+
+    output logic M_CLK,      // Clock do microfone
+    output logic M_LRSEL,    // Left/Right Select (Escolha do canal)
+
+    input  logic M_DATA      // Dados do microfone
+);
+
+
+logic clk_o;
+
+logic clk_core, rst_core;
+
+
+Controller #(
+    .CLK_FREQ           (50000000),
+    .BIT_RATE           (115200),
+    .PAYLOAD_BITS       (8),
+    .BUFFER_SIZE        (8),
+    .PULSE_CONTROL_BITS (32),
+    .BUS_WIDTH          (32),
+    .WORD_SIZE_BY       (4),
+    .ID                 (32'h7700006A),
+    .RESET_CLK_CYCLES   (20),
+    .MEMORY_FILE        (""),
+    .MEMORY_SIZE        (4096)
+) u_Controller (
+    .clk                (clk_o),
+    .rst_n              (CPU_RESETN),
+
+    // SPI signals
+    .sck_i              (sck),
+    .cs_i               (cs),
+    .mosi_i             (mosi),
+    .miso_o             (miso),
+
+    // SPI callback signals
+    .rw_i               (),
+    .intr_o             (),
+
+    // UART signals
+    .rx                 (rx),
+    .tx                 (tx),
+
+    // Clock, reset, and bus signals
+    .clk_core_o         (clk_core),
+    .rst_core_o         (rst_core),
+
+    // Barramento padrão (não AXI4-Lite)
+    .core_cyc_i         (),
+    .core_stb_i         (),
+    .core_we_i          (),
+    .core_addr_i        (),
+    .core_data_i        (),
+    .core_data_o        (),
+    .core_ack_o         ()
+
+    `ifdef ENABLE_SECOND_MEMORY
+    ,
+    // Segunda memória - memória de dados
+    .data_mem_cyc_i     (data_mem_cyc_i),
+    .data_mem_stb_i     (data_mem_stb_i),
+    .data_mem_we_i      (data_mem_we_i),
+    .data_mem_addr_i    (data_mem_addr_i),
+    .data_mem_data_i    (data_mem_data_i),
+    .data_mem_data_o    (data_mem_data_o),
+    .data_mem_ack_o     (data_mem_ack_o)
+    `endif
+);
+
+
+always_ff @(posedge clk) begin
+    if(!CPU_RESETN)
+        clk_o <= 1'b0;
+    else
+        clk_o <= ~clk_o;
+end
+
+endmodule