Alterando logica de enderecos

Alterando logica de enderecamento para acessar segunda memoria

Author: JN513

fpga/digilent_arty/run.tcl

@@ -1,9 +1,9 @@
 read_verilog "main.v"
-#read_verilog ../../modules/uart.v
-#read_verilog ../../modules/UART/rtl/uart_rx.v
-#read_verilog ../../modules/UART/rtl/uart_tx.v
-read_verilog ../../modules/spi.v;
-read_verilog ../../modules/SPI-Slave/rtl/spi_slave.v;
+read_verilog ../../modules/uart.v
+read_verilog ../../modules/UART/rtl/uart_rx.v
+read_verilog ../../modules/UART/rtl/uart_tx.v
+#read_verilog ../../modules/spi.v;
+#read_verilog ../../modules/SPI-Slave/rtl/spi_slave.v;
 read_verilog ../../src/fifo.v
 read_verilog ../../src/reset.v
 read_verilog ../../src/clk_divider.v
@@ -48,5 +48,6 @@ report_power -file digilent_arty_a7_power.rpt
 
 # write bitstream
 write_bitstream -force "./build/out.bit"
-
+#210203A7C2EE fpga 1
+#210203A7C654 fpga 2exit
 exit

fpga/xilinx_vc709/Makefile

@@ -1,4 +1,6 @@
-VIVADO_PATH = ${VIVADO_PATH}
+ifndef VIVADO_PATH
+	VIVADO_PATH=vivado
+endif
 
 all: ./build/out.bit
 

modules/spi.v

@@ -14,7 +14,7 @@ module SPI #(
     input wire miso,
 
     // SPI callback signals
-    input wire rw,
+    input wire  rw,
     output wire intr,
 
     // FIFOs signals
@@ -51,7 +51,7 @@ wire rst, busy, data_out_valid, busy_posedge;
 
 assign busy_posedge = (busy_sync[2:1] == 2'b01) ? 1'b1 : 1'b0;
 
-reg [1:0] read_state_machine, write_state_machine;
+reg [2:0] read_state_machine, write_state_machine;
 
 localparam IDLE              = 3'b000;
 localparam READ              = 3'b001;

src/controller.v

@@ -196,13 +196,13 @@ UART #(
 ) Uart(
     .clk  (clk),
     .reset(reset),
-
-    .uart_rx_empty(communication_rx_empty),
-    .uart_tx_empty(communication_tx_empty),
 
     .rx(rx),
     .tx(tx),
 
+    .uart_rx_empty(communication_rx_empty),
+    .uart_tx_empty(communication_tx_empty),
+
     .read (communication_read),
     .write(communication_write),
     .read_response (communication_read_response),

src/interpreter.v

@@ -232,7 +232,7 @@ always @(posedge clk) begin
 
             WRITE_IN_MEMORY: begin
                 memory_mux_selector <= 1'b0;
-                address <= {6'h0, communication_buffer[31:8], 2'b0};
+                address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0};
 
                 if(communication_rx_empty == 1'b0) begin
                     state <= READ_SECOND_PAGE_FROM_SERIAL;
@@ -261,7 +261,7 @@ always @(posedge clk) begin
 
             READ_FROM_MEMORY: begin
                 memory_mux_selector <= 1'b0;
-                address <= {6'h0, communication_buffer[31:8], 2'b0};
+                address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0};
                 memory_read <= 1'b1;
                 state <= MEMORY_READ;
             end
@@ -283,7 +283,7 @@ always @(posedge clk) begin
 
             WRITE_ACUMULATOR_IN_POS_N: begin
                 memory_mux_selector <= 1'b0;
-                address <= {6'h0, communication_buffer[31:8], 2'b0}; // ver alinhamento depois
+                address <= {communication_buffer[31], 6'h0, communication_buffer[30:8], 2'b0}; // ver alinhamento depois
                 write_data <= accumulator[31:0];
                 memory_write <= 1'b1;
                 state <= IDLE;