Integrando SPI

Author: JN513

.gitignore

@@ -16,4 +16,6 @@ env/
 site/
 build/
 webtalk*.log
-webtalk*.jou
+webtalk*.jou
+fpga/digilent_arty/usage_statistics_webtalk.xml
+fpga/digilent_arty/usage_statistics_webtalk.html

fpga/colorlight_i9/Makefile

@@ -21,6 +21,9 @@ all: ./build/out.bit
 		synth_ecp5 -json ./build/out.json -abc9 \
 	"
 
+#read_verilog ../../modules/spi.v; \
+#read_verilog ../../modules/SPI-Slave/rtl/spi_slave.v; \
+
 buildFolder:
 	mkdir -p build
 

fpga/digilent_arty/run.tcl

@@ -1,24 +1,26 @@
 read_verilog "main.v"
-read_verilog ../../modules/uart.v
-read_verilog ../../modules/UART/rtl/uart_rx.v
-read_verilog ../../modules/UART/rtl/uart_tx.v
+#read_verilog ../../modules/uart.v
+#read_verilog ../../modules/UART/rtl/uart_rx.v
+#read_verilog ../../modules/UART/rtl/uart_tx.v
+read_verilog ../../modules/spi.v;
+read_verilog ../../modules/SPI-Slave/rtl/spi_slave.v;
 read_verilog ../../src/fifo.v
 read_verilog ../../src/reset.v
 read_verilog ../../src/clk_divider.v
 read_verilog ../../src/memory.v
 read_verilog ../../src/interpreter.v
 read_verilog ../../src/controller.v
 
-read_verilog ../../Risco-5/src/core/alu_control.v
-read_verilog ../../Risco-5/src/core/alu.v
-read_verilog ../../Risco-5/src/core/control_unit.v
-read_verilog ../../Risco-5/src/core/core.v
-read_verilog ../../Risco-5/src/core/immediate_generator.v
-read_verilog ../../Risco-5/src/core/mux.v
-read_verilog ../../Risco-5/src/core/pc.v
-read_verilog ../../Risco-5/src/core/registers.v
-read_verilog ../../Risco-5/src/core/csr_unit.v
-read_verilog ../../Risco-5/src/core/mdu.v
+read_verilog ../../modules/Risco-5/src/core/alu_control.v
+read_verilog ../../modules/Risco-5/src/core/alu.v
+read_verilog ../../modules/Risco-5/src/core/control_unit.v
+read_verilog ../../modules/Risco-5/src/core/core.v
+read_verilog ../../modules/Risco-5/src/core/immediate_generator.v
+read_verilog ../../modules/Risco-5/src/core/mux.v
+read_verilog ../../modules/Risco-5/src/core/pc.v
+read_verilog ../../modules/Risco-5/src/core/registers.v
+read_verilog ../../modules/Risco-5/src/core/csr_unit.v
+read_verilog ../../modules/Risco-5/src/core/mdu.v
 
 
 read_xdc "digilent_arty.xdc"

modules/SPI-Slave

@@ -217,16 +217,15 @@ always @(posedge clk ) begin
                 readed     <= 1'b0;
                 data_in    <= tx_fifo_read_data;
 
-                if(zero == 1'b1) begin
-                    zero   <= 1'b0;
-                    reload <= 1'b1;
+                if(readed_trash == 1'b1) begin
+                    readed_trash <= 1'b0;
+                    reload       <= 1'b1;
                 end
             end 
         endcase
     end
 end
 
-// Read from uart and insert in RX queue
 always @(posedge clk ) begin
     rx_fifo_write <= 1'b0;
 

modules/spi.v

@@ -208,11 +208,38 @@ UART #(
     .read_response (communication_read_response),
     .write_response(communication_write_response),
 
-    .address   (32'h00000000),
     .write_data(communication_write_data),
     .read_data (communication_read_data)
 );
+/*
+SPI #(
+    .PAYLOAD_BITS(PAYLOAD_BITS),
+    .BUFFER_SIZE (BUFFER_SIZE),
+    .WORD_SIZE_BY(WORD_SIZE_BY)
+) Spi(
+    .clk  (clk),
+    .reset(reset),
+
+    .sck (sck),
+    .cs  (cs),
+    .mosi(mosi),
+    .miso(miso),
+
+    .rw  (rx),
+    .intr(intr),
+
+    .rx_fifo_empty(communication_rx_empty),
+    .tx_fifo_empty(communication_tx_empty),
 
+    .read (communication_read),
+    .write(communication_write),
+    .read_response (communication_read_response),
+    .write_response(communication_write_response),
+
+    .write_data(communication_write_data),
+    .read_data (communication_read_data)
+);
+*/
 Memory #(
     .MEMORY_FILE(MEMORY_FILE),
     .MEMORY_SIZE(MEMORY_SIZE)