Computer Engineer | FPGA & VLSI Design | Embedded Systems

📫 [email protected]  |  LinkedIn  |  GitHub

I'm a Graduate Research Assistant and current Master’s student in Electrical Engineering at UTRGV, working under Dr. Hasina Huq. I hold a Bachelor of Science in Computer Engineering from UTRGV, where I built a strong foundation in digital design, computer architecture, and embedded systems.

My interests center on FPGA, ASIC/VLSI, and front-end digital design, with a focus on RTL development, CPU architectures, and system-on-chip integration. I am passionate about semiconductor technologies and high-performance digital systems that power modern computing.

I enjoy building hardware that bridges theory and practice, from custom RISC-V CPU pipelines and transistor-level VLSI circuits to FPGA-based accelerators and real-time DSP systems. My goal is to design systems that are fast, efficient, and scalable, contributing to the next generation of computing hardware and semiconductor innovation.

I believe in engineering with purpose: using hardware design to push the boundaries of performance while enabling meaningful real-world applications.

Building a real-time FPGA DSP pipeline with autotune, reverb, and harmonic enhancement, using a Python-to-Verilog testbench (3.6M+ samples) and validating <15 ms latency on real trumpet recordings.

Designing a 32-bit, 5-stage pipelined RISC-V CPU with hazard detection and forwarding, expanding from a custom ISA simulator to Verilog RTL targeting FPGA implementation.

Implemented a 12-state Moore FSM with debounced inputs, clock division, and LED feedback on the Nexys A7-100T FPGA, fully verified with modular Verilog test sequences.

A collection of CMOS digital circuits including XOR gates, adders, and an 8-bit ripple-carry adder, designed and simulated using Cadence Virtuoso, demonstrating transistor-level digital design expertise.

Built a TCP/IP client-server interface to control LEDs via HPS–FPGA integration on the DE1-SoC, achieving sub-second response time and 100% command reliability over 30+ tests.

🔬 Graduate Research Assistant @ UTRGV (Present)
Conducting research in semiconductor materials and device fabrication under Dr. Hasina Huq, focusing on GaN thin-film deposition and characterization.

🧑‍🔬 Teaching Assistant @ UTRGV (2025)
Managed 3 weekly lab sessions on analog & digital circuits, instrumentation, and measurement. Provided hands-on troubleshooting that reduced lab completion times by nearly 50%.

🧪 Research Assistant @ UTRGV (2025)
Developed Federated Incremental Gaussian Process (F-IGP) algorithms with 1K+ update cycles. Simulated 18.5K+ samples across multi-agent networks, achieving a 72% reduction in NLL and 48% drop in MSE. Contributed as co-author on a paper submitted to the Asilomar Conference on Signals, Systems, and Computers.

🧬 Undergraduate Researcher @ UTRGV (2024)
Led a 4-person team to build a real-time facial recognition system for classroom attentiveness using a custom CNN. Processed 4K+ labeled samples, reaching >90% accuracy, and presented results to 200+ K-12 students.

🚗 NSF REU (2023)
Collaborated with researchers in a 10-week program focused on autonomous vehicle safety. Supported ML-based decision-making research aimed at reducing conflict zones by 50%.

📫 I’m always open to discussing research collaborations, hardware/FPGA design projects.

Feel free to reach out at [email protected].