121 suggestions 1 2 #127
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121 suggestions 1 2 #127
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Replace switch-case logic in ADC interrupt with circular linked list for improved performance and reduced code size. Based on florentbr's optimization suggestion #1 from issue #113. - Add adc_ctx_t structure with minimal memory footprint - Implement circular linked list for 6 ADC channels - Eliminate branching in time-critical ISR code - Maintain exact same functionality as original implementation
Reorganize code structure for better maintainability: - Remove duplicate ADC definitions from top of file - Keep all ADC optimization code together near the ISR - Improve code organization and readability No functional changes, just code organization improvement.
- Changed DC offset from per-cycle LPF to per-sample EMA filter - Use Q16.16 fixed-point format for efficient calculation - Enable ADLAR=1 for left-aligned ADC results - Simplify voltage/current sample processing - Reduce computational overhead in ISR
Move opening brace of the else branch to a new line for consistent brace style in processing.cpp
…n metadata - Replace two type-specific overloads with a single constexpr template<typename T, size_t N> initializeArray(T (&array)[N], T value) to remove duplication and support any array element type. - Expand and clarify Doxygen comments for initializeArray (usage, template params, notes). - Update version.h CURRENT_TIME and reset
- Add mult_asm.h with optimized 16x16->32 signed multiplication (~3x faster) - Integrate assembly multiplication in processCurrentRawSample() and processVoltage() - Fix ADMUX timing issue (#125): move ADMUX assignment to end of ISR - Change CT filter condition to 'if constexpr' for guaranteed dead code elimination - Add unit tests for assembly multiplication functions Performance improvements: - ISR multiplication: ~15-20 cycles vs ~50+ cycles (library calls) - Zero overhead for disabled CT filtering (compile-time elimination) - Proper ADMUX timing: 128+ CPU cycles after trigger event per datasheet Based on florentbr's optimization suggestions and ATmega328p datasheet requirements.
- Add multU16x16_to32 unsigned multiplication function - Change l_sum_Vsquared from int32_t to uint32_t (V² always positive) - Rename mult16x16_to32 to multS16x16_to32 for clarity - Add comprehensive test coverage for unsigned multiplication - Add voltage accumulation overflow tests (220 lines) - Validates current shift strategy is safe for all datalog periods - Proves uint32_t provides 2x headroom vs int32_t (4.3B vs 2.1B) Related: #121, #125, PR #127
Make spacing consistent around template parameters and static_cast uses, and tidy up stray blank/whitespace in test_main.cpp for the voltage accumulation overflow tests.
…rocessCurrentRawSample Add inline declarations (uint16_t sample parameter) in both header sections so the function signatures match the always_inline/optimized declarations and the Doxygen variants, avoiding mismatches.
…hase into 121-suggestions-1-2
…t scaling and tests - In ISR-heavy paths, reduce voltage/current samples by >>2 (to 14-bit / x16 scale) prior to multS16x16_to32 to improve efficiency on 8-bit MCUs. - Update scaling shifts to match the new pre-shift: - real power multiplication: use filt >>2 then mult, final shift >>8 - V² accumulation: use filt >>2 then mult, final shift >>8 for <=10s or >>12 for >10s (effectively reducing previous right-shifts by 4 bits while preserving numeric scale) - Update test/embedded/test_voltage_accumulation to use the 14-bit pre-shift strategy, adjust test cases and messages (including overflow demo) and refresh conclusions.
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@florentbr Good news, at least for voltage on L1. The value are still correct ;-) From time to time, there's a value of "0.81" for V2 and V3, even nothing is wired. Same exact effet with the "original" version :D |
* fix: update ADMUX at end of ADC ISR to meet ATmega328P timing Move ADMUX write to the end of the ADC_vect ISR so at least 128 CPU cycles have passed since the trigger event (per ATmega328P datasheet). Prevents premature channel switching and ensures correct sampling timing. * #126 (comment)
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