Skip to content
View ChinniSravanthhi's full-sized avatar

Block or report ChinniSravanthhi

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
ChinniSravanthhi/README.md

Hi πŸ‘‹ I'm Lalam Chinni Sravanthi

About me

  • πŸ”­ I completed my B.Tech degree in Electronics and Communication Engineering from RGUKT IIIT Srikakulam.
  • 🌱 I’m currently learning about VLSI design Advanced Protocols like PCIE, Ethernet, USB, RISC V and DDR
  • πŸ‘― I’m looking to collaborate on innovative projects related to VLSI design(RTL, DV ), AMBA Protocols, Communication Protocols.
  • πŸ€” I’m looking for help with real-world applications of my skills and internship/JOB opportunities in the VLSI Semoconductor field.
  • πŸ’¬ Ask me about VLSI design, RTL Design or any projects related to VLSI Front-end DV role.
  • πŸ“« How to reach me: [email protected]
  • πŸ˜„ Pronouns: She/her
  • ⚑ Fun fact: I enjoy coding in Verilog and have a passion for solving complex problems!

Popular repositories Loading

  1. ChinniSravanthhi ChinniSravanthhi Public

    Hello world, this is my profile

  2. Verilog-RTL-Coding---Combinational-Circuits Verilog-RTL-Coding---Combinational-Circuits Public

    "Mastering RTL-Coding : From Fundamentals to Advanced Programming Techniques using Verilog,System Verilog and UVM"

    Verilog

  3. Verilog-RTL-Coding---Sequential-Circuits Verilog-RTL-Coding---Sequential-Circuits Public

    Verilog