Digital Systems Engineering - COE758

This course covers the basics of advanced computing systems. The emphasis is in understanding the system architecture around the processor and the different components of modern digital systems. The course covers Memory hierarchy including Main memory, Cache and Virtual memory. It covers the Interfacing of processors and peripherals including Input / Output devices: Video-Output subsystem and Hard Disk Drives. The course gives classification of buses and description of major concepts of bus organization and protocols. This course is taken at TMU, formally known as Ryerson. (COE758)

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-> F2025 (Fall)

Contents Covered:

• Memory hierarchy including Main memory, Cache and Virtual memory
• Memory subsystem organization and bus design between CPU, Cache, and Main Memory (SDRAM)
• Address and data line calculations for memory subsystems
• Control signal identification and bandwidth analysis
• Virtual memory and cache interaction including TLB (Translation Lookaside Buffer) and Page Tables
• Address translation from virtual to physical addresses
• Cache organization (set-associative, direct-mapped) and replacement policies (NRU, LRU)
• Processor and peripheral interfacing
• Video-Output subsystem (VGA timing, synchronization signals, video RAM)
• VGA timing specifications and synchronization signal generation (Vsync, Hsync)
• Video RAM calculations for graphic and character modes
• Pixel clock generation and video memory access time requirements
• Hard Disk Drive interfacing
• Bus organization and protocols
• Bus arbitration schemes (centralized parallel, centralized serial, distributed)
• Direct Memory Access (DMA) and burst mode transfers
• SCSI bus protocols and bandwidth calculations
• FPGA design and implementation using Xilinx ISE tools
• VHDL programming for digital systems
• ChipScope debugging and BRAM utilization

Laboratory

• Project 1: On-Chip Memory Controller (Cache Controller) - Design and implementation of cache controller using FPGA. This project involves designing a cache controller that interfaces between CPU and SDRAM, implementing cache organization, replacement policies, and bus protocols.

• Project 2: Video-signal generator for VGA-monitor (Pong Game) - Design of video output subsystem with VGA display. This project involves implementing a complete video output system including VGA timing generation, video RAM management, and real-time graphics rendering for a Pong game.

Final Project

The course culminates with comprehensive design projects that integrate the concepts learned throughout the semester. Projects 1 and 2 serve as the main design projects, covering memory subsystem design and video output subsystem design respectively. These projects demonstrate practical application of digital systems engineering principles including memory hierarchy, bus organization, and peripheral interfacing using FPGA platforms.