π Final Year B.Tech - Electronics and Communication Engineering, VIT Vellore
π¬ Research & Development Head - ADG-VIT Technical Club
π Domain Focus: VLSI Design, Digital Verification, RTL to GDSII Flow
π οΈ Specialization: Embedded Systems, FPGA Prototyping, EDA Tool Automation
- Technology: TSMC 32nm Process
- Tools: Synopsys Design Compiler, RTL Synthesis
- Features: Complete RTL to GDSII implementation
- Verification: Comprehensive testbench with functional coverage
- Platform: Raspberry Pi 5 + CNN Integration
- AI Model: EfficientNetV2-L for soil classification
- Hardware: Custom sensor integration with real-time processing
- Hardware: ESP32-CAM, RFID, Ultrasonic Sensors
- Features: Cloud integration, servo motor control
- Design: Complete embedded system architecture
- Components: PIR sensors, Arduino, DC motor interfacing
- Control: Real-time motion detection and response system
- Leadership: Leading innovation projects combining hardware and software
- Mentorship: Guiding junior members in digital design methodologies
- Background: Previous ML team member with cross-domain expertise
- Focus: Edge AI and embedded vision systems
module current_learning;
reg [31:0] focus_areas;
initial begin
focus_areas = {
"Advanced UVM Verification",
"RTL to GDSII Automation",
"High-Speed Digital Design"
};
$display("π± Always learning, always growing!");
end
endmoduleπ§ Email: [email protected]
π« Institution: Vellore Institute of Technology, Vellore
π Location: Vellore, Tamil Nadu, India
- π¬ RTL Design & Verification: Advanced digital design methodologies
- β‘ EDA Tool Automation: Python/TCL scripting for design flows
- π οΈ FPGA Prototyping: Rapid prototyping and validation
- π§ Physical Design: Place & Route, Timing Closure, Power Analysis
- π€ Hardware-ML Integration: Edge AI and embedded acceleration
β Star my repositories if you find them useful! β
π Open to collaborations in VLSI Design, Verification, and EDA Tool Development π
