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Merge branch 'main' into jumerckx/pdl-to-pdl-interp-eqsat
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flake.lock

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// RUN: xdsl-opt --split-input-file -p "riscv-allocate-registers{allocation_strategy=LivenessBlockNaive force_infinite=true}" %s | filecheck %s
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// check that infinite registers are used
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riscv_func.func @main() {
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%0, %1 = "test.op"() : () -> (!riscv.reg, !riscv.reg)
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%2, %3 = riscv.parallel_mov %0, %1 [32, 32] : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
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riscv_func.return
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}
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// CHECK: builtin.module {
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// CHECK-NEXT: riscv_func.func @main() {
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// CHECK-NEXT: %0, %1 = "test.op"() : () -> (!riscv.reg<j_0>, !riscv.reg<j_1>)
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// CHECK-NEXT: %2, %3 = riscv.parallel_mov %0, %1 [32, 32] : (!riscv.reg<j_0>, !riscv.reg<j_1>) -> (!riscv.reg<j_0>, !riscv.reg<j_1>)
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// CHECK-NEXT: riscv_func.return
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// CHECK-NEXT: }
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// CHECK-NEXT: }

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