Update the data model

[richardissuperman]

ParamCGRA was intended for a single CGRA design, now we are migrating to multi cgra, the data model shall evolve to

class ParamMultiCGRA:
    def __init__(self, rows, cols):
        self.rows = rows
        self.cols = cols
        self.cgras = [[ParamCGRA(r, c) for c in range(cols)] for r in range(rows)]

class ParamCGRA

and each model shall hold a observer to observe data change and update its corresponding UI as well

 def bind(self, key, callback):
        if key not in self._observers:
            self._observers[key] = []
        self._observers[key].append(callback)

the bind shall help to trigger the corresponding UI.

Each param shall have a scope of view (the parent of the UI view component in tkinter) and only update the minimized UI as possible

[richardissuperman]

first test commit in test branch to move every outside of ui python

fae8673

[richardissuperman]

next step is to replace all the legacy code in UI file which reference oldCGRA, gloabl etc to use the multi cgra model class to fetch the right CGRA model ,and update/refresh UI to show the current selected CGRA.

[richardissuperman]

second test commit to create multi-cgra model , and encapuslate per-cgra model param

0c69852

[richardissuperman]

Next step is to

1. update multi-cgra param when cgra rows and cols are updated
2. reset selected cgra ui when re-select

[richardissuperman]

third commit to use multi-cgra model object to refresh per-cgra model UI, this approach will have memory on which per-cgra model changes to what. and persist the UI when user click.

cca98a4

below Gif shows user clicks cgra 0, update tiles, and switch to cgra 1, titles update, clicked back to cgra 0, titles update again

[tancheng]

Excellent~!

[richardissuperman]

Next step is

update multi-cgra param when cgra rows and cols are updated

[richardissuperman]

Last step done

76c3553

In this commit, I update the data model for the upper multi-cgra-param and refresh the UI accordingly.

1. If per-cgra model changes, only per-cgra ui refresh
2. if multi-cgra changes, for exameple row/col changes, the entire UI refresh accordingly.

Later improvement, since the entire UI shifts, consider launching the loading page again in this case

[richardissuperman]

@yuqisun @tancheng please let me know what you think, if its ok i will start making pull request

[tancheng]

LGTM~!

[richardissuperman]

#68

[tancheng]

Hi @richardissuperman and @yuqisun, I am thinking leverging VS code as master, but somehow VS code can invoke our GUI (invoking docker or VS code running in a linux docker if possible?) and leverage VS code's builtin support of AI agents: https://code.visualstudio.com/blogs/2025/04/07/agentMode.

In this way, we don't need build our own GUI or agent interface to interact with GUI. WDYT?

[yuqisun]

Need user to input LLM api key themselves, and supports models below(I'm using deepseek-chat):

[tancheng]

deepseek-chat is free?

I believe it allows to integrate our own model (e.g., downloaded and deployed locally)?

[yuqisun]

deepseek-chat is chargeable. Integrate local model should be also good just make sure it follows openai API style, but I'm afraid it's hard to afford the performance.

[tancheng]

it's hard to afford the performance.

What perf you are referring to? The model is too huge to run locally? Some user might also have their own powerful GPU equipped locally.

[yuqisun]

Yes, the speed and comprehension ability.

Should be good if users own strong machine to run models, as per the model-recommendations from openhands, guess at least 20~30B model is required.

[richardissuperman]

Hi Cheng I think thats helpful at the code base level, but not gonna be helpful for longer term vision? Example: 1. If you ask the agent please help to build a 3X3 multi cgra instead of 4X4 I believe this agent can do that by executing our python code with 3X3 parameters. 2. But if you say some vague command like : I want to build a multi-cgra with xxx constraint and save power in xxx area. (recall we had a brief conversation about this vague commands ) I dont think this code agent can help? Above is my naive understanding

…

On Thu, May 15, 2025 at 7:25 PM Cheng Tan ***@***.***> wrote: Hi @richardissuperman <https://github.com/richardissuperman> and @yuqisun <https://github.com/yuqisun>, I am thinking leverging VS code as master, but somehow VS code can invoke our GUI (invoking docker or VS code running in a linux docker if possible?) and leverage VS code's builtin support of AI agents: https://code.visualstudio.com/blogs/2025/04/07/agentMode. In this way, we don't need build our own GUI or agent interface to interact with GUI. WDYT? — Reply to this email directly, view it on GitHub <#67 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABI5PAJQ4MB34D4GEWDKFGT26VEBPAVCNFSM6AAAAAB3AQIJ7GVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTGMJWGU2TMNQ> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[tancheng]

I thought VS code supports MCP https://modelcontextprotocol.io/introduction, so easily to enable interaction across agents. I just try to leverage VS code as an interface to enable that interaction, e.g., I want to build a multi-cgra with xxx constraint and save power in xxx area. VS code would parse this sentence and issue MCP command/pkt to our GUI or python functions.

Yes, our python interface should be able to decode that MCP command anyways. I think I kind of treating VS code as an OS in this context..

[richardissuperman]

Oh mcp server! That may work, let me chat with shumin on this, she was working on related topics

…

On Thu, May 15, 2025 at 10:26 PM Cheng Tan ***@***.***> wrote: I thought VS code supports MCP https://modelcontextprotocol.io/introduction, so easily to enable interaction across agents. I just try to leverage as an interface to enable that interaction, e.g., I want to build a multi-cgra with xxx constraint and save power in xxx area. VS code would parse this and issue MCP command/pkt to our GUI or python functions. Yes, our python interface should be able to decode that MCP command anyways. I think I kind of treating VS code as an OS in this context.. — Reply to this email directly, view it on GitHub <#67 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/ABI5PAMREREUUCXNKLLQLTT26VZJTAVCNFSM6AAAAAB3AQIJ7GVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTGMJWGY2TAMI> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[richardissuperman]

#70

a test demo with MCP integrated.

[yuqisun]

++ @zsjiang99 for visibility

[richardissuperman]

Hi @zsjiang99 @yuqisun @tancheng

I had some brainstorm sessions today and have some ideas about using LLM agent for CGRA design

1. Generate random multi CGRA configuration (size, PE, SPM etc)

2. Run tests using above configurations, get the corresponding reports

3. After i gather the results, use LLM agent to compare results with configuration, the prompt will be like

"I asked you to use xxxx configs to generate a multi cgra design, the estimate power consumption is xxx, compared to the current config which power consumption is xxx"

Using above experiment data to generate prompts to the model.

4. after that user can use the model+ prompt to do following design by using natural language.

@yuqisun one quick question i was trying to use master branch to get the synthesis working, but i saw below error

Am i having a wrong configuration in the docker file or my path setting is wrong?

thanks!

[yuqisun]

Hi @richardissuperman ,

1. To fix issue:
   Looks there's no VectorCGRA in your env, please try with git submodule update --init to update submodules. And we have name change from CGRATemplateRTL_* -> CgraTemplateRTL_*. So need change the names in 'mode_dark_light.py' and mflowgen, refer to:

https://github.com/tancheng/CGRA-Flow/pull/69/files#diff-17b2a32393526982665ba098429ab2489e47cebfdf2995dd2b9453506737e859
(didn't merge yet as there's issue which very slow the synthesis process: tancheng/VectorCGRA#148), will talk in weekly meeting. Can temp skip by set LHS array index as 0.

and
tancheng/mflowgen#1 (BTW, @tancheng , could you help confirm if good to merge tancheng/mflowgen#1 to update file name.)

2. To synthesis:
   If you need run synthesis only (with old code), can try with cgra/cgra-flow:20241028 image for now, both are single CGRA template.(I'm workong on multi)

3. For the idea:
   I'm thinking if the contribution is enough if using LLM only for this.(Also depends on the results).
   Whether we can fine tune or much easier --- to build some decision tree for features -> area, features -> power and box them as MCP servers, then LLM calls them as hints to design? WDYT? And I'm think what is the final goal, if we claim LLM can do all, reviewers may challenge a lot, how about a human-in-loop mode and agent only helps get quickly to be in an available area(solutions/hypothesis), then human completes the last step? Too low? Not sure, need discuss with experts. @zsjiang99 is there better ideas from you or enlighten by the papers?

Thanks,

[richardissuperman]

@yuqisun does it exist

from VectorCGRA.cgra.test.CgraTemplateRTL_test import * ?

I checked the PR

https://github.com/tancheng/CGRA-Flow/pull/69/files#diff-17b2a32393526982665ba098429ab2489e47cebfdf2995dd2b9453506737e859

but in that branch there is no such file as

VectorCGRA.cgra.test.CgraTemplateRTL_test

[yuqisun]

Hi @richardissuperman ,

Please checkout https://github.com/tancheng/VectorCGRA/tree/synthesis_test branch for VectorCGRA module.

Thanks,

[tancheng]

tancheng/mflowgen#1 approved and merged, thanks~!

[zsjiang99]

Hi, I've put together a simple initial version of a CGRA framework. The details are in our email—hope it can serve as a simple reference.
Thanks！

[yuqisun]

Hi all,

Let you know, please can use https://github.com/tancheng/VectorCGRA/tree/synthesis_test branch for synthesis test.

Thanks,

[zsjiang99]

Hi, @yuqisun @richardissuperman I noticed that this CGRA-Flow can directly generate SystemVerilog code. Does this mean that we don't need to focus on code generation, and can instead concentrate more on the architecture design? : )

[zsjiang99]

I also want to ask if there's any possibility for further optimization in the code generation part. :)

[tancheng]

let's start from arch design.

The generated Verilog code could definitely be improved, as the arch design (written in PyMTL) is not optimized, i.e., sequential for loop leading to long latency/critical path, unnecessary wires/ports, separate ports that can actually be bundled to be more dense and improve the area.

• I believe we can later use LLM to refactor the generated Verilog (i.e., agent: generated Verilog refactor)
• And then we can use LLM to even rewrite the architecture design (i.e., agent: pymtl rewriter, or even arch designer)

[zsjiang99]

OK, thank you, Dr.Tan. :)

[yuqisun]

Hi @tancheng ,

I'm trying to synthesis 2x2 cgras and 2x2 tiles, it has been running over 6 hours and still running.

I stated verilog of single CGRA (2x2) to compare, can see the quantities (# of wires, memory bits, cells...) are approximately 4 times difference, so looks make sense right (2x2_2x2 with single_cgra_2x2)? But the synthesis time is much longer than single.

Looks as the complexity of the Verilog increases, the difficulty of synthesis does not grow linearly but rather exponentially? If so, may we test with single CGRA arch to collect data instead of multi CGRA? --- Also concern about large single CGRA (i.e., 8x8, 12x12, 16x16), will try that.

Single cgra synthesis time details: tancheng/VectorCGRA#150 (comment)

stat 2x2_2x2:

   Number of wires:             2129420
   Number of wire bits:         33361662
   Number of public wires:       97388
   Number of public wire bits:  2630742
   Number of memories:             552
   Number of memory bits:       179000
   Number of processes:          11002
   Number of cells:             908456
     $add                       301704
    ...

More info: verilog_stat_2x2_2x2.txt

stat single_2x2:

   Number of wires:             562343
   Number of wire bits:         8790439
   Number of public wires:       19845
   Number of public wire bits:  613371
   Number of memories:             145
   Number of memory bits:        42696
   Number of processes:           2481
   Number of cells:             262305
     $add                        99991
    ...

More info: verilog_stat_1_cgra_2x2.txt

Verilog(/WORK_REPO/CGRA-Flow/tools/mflowgen/designs/cgra/rtl/outputs): design.v.txt

[tancheng]

Right, I would say we start from single cgra with multiple tiles for our design agent, but just make sure we use the multi-cgra template to do it, instead of old single cgra template.

[tancheng]

And are you able to use the multi-cgra template to get a layout of 1-cgra-2x2-tiles via openroad? Looking forward to it.

[yuqisun]

Hi @tancheng ,

1. Multi-CGRA UI connects to template and synthesis looks good (276s):

=== CgraTemplateRTL ===

   Number of wires:             950635
   Number of wire bits:         1522998
   Number of public wires:      950635
   Number of public wire bits:  1522998
   Number of ports:                 17
   Number of port bits:            894
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:             982376

2. I'm running Place and Route now, will check result later.

3. But got an error when test map kernel DFG, error below. Looks it's similar as Error occurs when test the "run.sh" CGRA-Mapper#5?
   But I tried manually copy https://github.com/tancheng/CGRA-Mapper/blob/master/test/kernels/fir/param.json to

   CGRA-Flow/mode_dark_light.py

   Lines 1275 to 1293 in 82fd6e7

   	genDFGJson = {
   	"kernel": paramCGRA.targetKernelName,
   	"targetFunction": False,
   	"targetNested": True,
   	"targetLoopsID": [0],
   	"doCGRAMapping": False,
   	"row": paramCGRA.rows,
   	"column": paramCGRA.columns,
   	"precisionAware": False,
   	"heterogeneity": False,
   	"isTrimmedDemo": True,
   	"heuristicMapping": True,
   	"parameterizableCGRA": True,
   	"diagonalVectorization": False,
   	"bypassConstraint": 8,
   	"isStaticElasticCGRA": False,
   	"ctrlMemConstraint": 200,
   	"regConstraint": 12,
   	}

Still error. Any idea if I miss something?

param.json

opt-12 err: b'*** reach target loop ID: 0\n... done detected loops.size(): 1\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** current basic block: ; First Inst: br label %4\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because instruction " br label %4" is out of the scope (target loop).\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because basic block "" is out of the scope (target loop).\n\xe2\x94\x82\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** current basic block: ; First Inst: %5 = phi i64 [ 0, %3 ], [ %13, %4 ]\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %5 = phi i64 [ 0, %3 ], [ %13, %4 ]" (ID: 0)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ]" (ID: 1)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %7 = getelementptr inbounds float, float* %0, i64 %5" (ID: 2)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %8 = load float, float* %7, align 4, !tbaa !2" (ID: 3)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %9 = getelementptr inbounds float, float* %2, i64 %5" (ID: 4)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %10 = load float, float* %9, align 4, !tbaa !2" (ID: 5)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %11 = fmul float %8, %10" (ID: 6)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %12 = fadd float %6, %11" (ID: 7)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %13 = add nuw nsw i64 %5, 1" (ID: 8)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " %14 = icmp eq i64 %13, 32" (ID: 9)\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ " br i1 %14, label %15, label %4, !llvm.loop !6" (ID: 10)\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ basic block "" got ID: 0\n\xe2\x94\x82\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** current basic block: ; First Inst: store float %12, float* %1, align 4, !tbaa !2\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because instruction " store float %12, float* %1, align 4, !tbaa !2" is out of the scope (target loop).\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because instruction " ret void" is out of the scope (target loop).\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because basic block "" is out of the scope (target loop).\n\xe2\x94\x82\n\xe2\x94\x82\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** curBB: ; First Inst: %5 = phi i64 [ 0, %3 ], [ %13, %4 ]\n\xe2\x94\x82 \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 *** find terminator instruction of curBB: br i1 %14, label %15, label %4, !llvm.loop !6\n\xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignore sucBB ""\n\xe2\x94\x82 \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 *** into sucBB ""\n\xe2\x94\x82 \xe2\x94\x82 \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 Type: first inst of a BB.\n\xe2\x94\x82 \xe2\x94\x82 \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 ctrl flow point to: %5 = phi i64 [ 0, %3 ], [ %13, %4 ]; In BB: \n\xe2\x94\x82 \xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ construct ctrl flow: br i1 %14, label %15, label %4, !llvm.loop !6-> %5 = phi i64 [ 0, %3 ], [ %13, %4 ]\n\xe2\x94\x82 \xe2\x94\x82 \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 Type: inst without [intra-basicblock & intra-iteration data flow] nor [ctrl flow] pointed to it.\n\xe2\x94\x82 \xe2\x94\x82 \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 ctrl flow point to: %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ]; In BB: \n\xe2\x94\x82 \xe2\x94\x82 \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ construct ctrl flow: br i1 %14, label %15, label %4, !llvm.loop !6-> %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ]\n[detected one cycle] head: %5 = phi i64 [ 0, %3 ], [ %13, %4 ]\ncycle edge: { %5 = phi i64 [ 0, %3 ], [ %13, %4 ] } -> { %13 = add nuw nsw i64 %5, 1 } (0 -> 8)\ncycle edge: { %13 = add nuw nsw i64 %5, 1 } -> { %5 = phi i64 [ 0, %3 ], [ %13, %4 ] } (8 -> 0)\n[detected one cycle] head: %5 = phi i64 [ 0, %3 ], [ %13, %4 ]\ncycle edge: { %5 = phi i64 [ 0, %3 ], [ %13, %4 ] } -> { %13 = add nuw nsw i64 %5, 1 } (0 -> 8)\ncycle edge: { %13 = add nuw nsw i64 %5, 1 } -> { %14 = icmp eq i64 %13, 32 } (8 -> 9)\ncycle edge: { %14 = icmp eq i64 %13, 32 } -> { br i1 %14, label %15, label %4, !llvm.loop !6 } (9 -> 10)\ncycle edge: { br i1 %14, label %15, label %4, !llvm.loop !6 } -> { %5 = phi i64 [ 0, %3 ], [ %13, %4 ] } (10 -> 0)\n[detected one cycle] head: %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ]\ncycle edge: { %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ] } -> { %12 = fadd float %6, %11 } (1 -> 7)\ncycle edge: { %12 = fadd float %6, %11 } -> { %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ] } (7 -> 1)\n(8) %13 = add nuw nsw i64 %5, 1, level: 0\n(9) %14 = icmp eq i64 %13, 32, level: 1\n(10) br i1 %14, label %15, label %4, !llvm.loop !6, level: 2\n(0) %5 = phi i64 [ 0, %3 ], [ %13, %4 ], level: 3\n(2) %7 = getelementptr inbounds float, float* %0, i64 %5, level: 4\n(4) %9 = getelementptr inbounds float, float* %2, i64 %5, level: 4\n(3) %8 = load float, float* %7, align 4, !tbaa !2, level: 5\n(5) %10 = load float, float* %9, align 4, !tbaa !2, level: 5\n(6) %11 = fmul float %8, %10, level: 6\n(7) %12 = fadd float %6, %11, level: 7\n(1) %6 = phi float [ 0.000000e+00, %3 ], [ %12, %4 ], level: 8\nterminate called after throwing an instance of \'nlohmann::detail::type_error\'\n what(): [json.exception.type_error.302] type must be boolean, but is null\nPLEASE submit a bug report to https://bugs.llvm.org/ and include the crash backtrace.\nStack dump:\n0.\tProgram arguments: opt-12 -load ../../CGRA-Mapper/build/src/libmapperPass.so -mapperPass ./kernel.bc\n1.\tRunning pass \'Function Pass Manager\' on module \'./kernel.bc\'.\n2.\tRunning pass \'DFG Pass Analyse\' on function \'@_Z6kernelPfS_S_\'\nStack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var LLVM_SYMBOLIZER_PATH to point to it):\n/lib/x86_64-linux-gnu/libLLVM-12.so.1(_ZN4llvm3sys15PrintStackTraceERNS_11raw_ostreamEi+0x31)[0x7f444c4fe2a1]\n/lib/x86_64-linux-gnu/libLLVM-12.so.1(_ZN4llvm3sys17RunSignalHandlersEv+0x50)[0x7f444c4fc3d0]\n/lib/x86_64-linux-gnu/libLLVM-12.so.1(+0xd739ad)[0x7f444c4fe9ad]\n/lib/x86_64-linux-gnu/libc.so.6(+0x42520)[0x7f444b271520]\n/lib/x86_64-linux-gnu/libc.so.6(pthread_kill+0x12c)[0x7f444b2c59fc]\n/lib/x86_64-linux-gnu/libc.so.6(raise+0x16)[0x7f444b271476]\n/lib/x86_64-linux-gnu/libc.so.6(abort+0xd3)[0x7f444b2577f3]\n/lib/x86_64-linux-gnu/libstdc++.so.6(+0xa2b9e)[0x7f444b601b9e]\n/lib/x86_64-linux-gnu/libstdc++.so.6(+0xae20c)[0x7f444b60d20c]\n/lib/x86_64-linux-gnu/libstdc++.so.6(+0xae277)[0x7f444b60d277]\n/lib/x86_64-linux-gnu/libstdc++.so.6(+0xae4d8)[0x7f444b60d4d8]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZN8nlohmann6detail9from_jsonINS_10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS_14adl_serializerES4_IhSaIhEEEEEEvRKT_RNSF_9boolean_tE+0xf6)[0x7f4449083478]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZNK8nlohmann6detail12from_json_fnclINS_10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS_14adl_serializerES5_IhSaIhEEEERbEEDTcl9from_jsonfp_cl7forwardIT0_Efp0_EEERKT_OSH_+0x36)[0x7f444907a694]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZN8nlohmann14adl_serializerIbvE9from_jsonIRKNS_10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaS0_S5_IhSaIhEEEEbEEDTcmclL_ZNS_12_GLOBAL__N_19from_jsonEEcl7forwardIT_Efp_Efp0_Ecvv_EEOSI_RT0_+0x40)[0x7f444907455d]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZNK8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS_14adl_serializerES2_IhSaIhEEE8get_implIbLi0EEET_NS_6detail12priority_tagILj0EEE+0x36)[0x7f4449069cd2]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZNK8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS_14adl_serializerES2_IhSaIhEEE3getIbbEEDTcldtcl7declvalIRKSC_EE8get_implIT0_EcvNS_6detail12priority_tagILj4EEEilEEEv+0x2b)[0x7f444906436b]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZNK8nlohmann10basic_jsonISt3mapSt6vectorNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEblmdSaNS_14adl_serializerES2_IhSaIhEEEcvT_IbLi0EEEv+0x1c)[0x7f4449062ce4]\n../../CGRA-Mapper/build/src/libmapperPass.so(_ZN4CGRAC1EiibPNSt7__cxx114listINS0_12basic_stringIcSt11char_traitsIcESaIcEEESaIS6_EEEbPSt3mapIS6_PNS1_IiSaIiEEESt4lessIS6_ESaISt4pairIKS6_SD_EEEbi+0x717)[0x7f44490b5093]\n../../CGRA-Mapper/build/src/libmapperPass.so(+0x12ca1e)[0x7f4449059a1e]\n/lib/x86_64-linux-gnu/libLLVM-12.so.1(_ZN4llvm13FPPassManager13runOnFunctionERNS_8FunctionE+0x3a0)[0x7f444c6329b0]\n/lib/x86_64-linux-gnu/libLLVM-12.so.1(_ZN4llvm13FPPassManager11runOnModuleERNS_6ModuleE+0x33)[0x7f444c638563]\n/lib/x86_64-linux-gnu/libLLVM-12.so.1(_ZN4llvm6legacy15PassManagerImpl3runERNS_6ModuleE+0x3a8)[0x7f444c632fb8]\nopt-12(main+0x2ff1)[0x432b11]\n/lib/x86_64-linux-gnu/libc.so.6(+0x29d90)[0x7f444b258d90]\n/lib/x86_64-linux-gnu/libc.so.6(__libc_start_main+0x80)[0x7f444b258e40]\nopt-12(_start+0x25)[0x41f9f5]\nAborted (core dumped)\n'

[tancheng]

Thanks @yuqisun,

1. What template? your newly created multi-cgra-template or original cgra-template? The SVerilog window/panel shows CgraTemplateRTL.v. I thought we mentioned create new MultiCgraTemplateRTL.py?
2. Sounds good.
3. parameterizableCGRA: True requires some other input file iirc? It reports [json.exception.type_error.302] type must be boolean, but is null, I think you can debug the c++ to figure out what is missing, it seems not compiler/mapping issue, just json read/parse issue

[yuqisun]

Hi,

1. Yes, MeshMultiCgraTemplateRTL_test.py is created, but still make it output name - CgraTemplateRTL for now to save time, once verified all is good, will change the name and change in the UI, mflowgen and openroad config file accordingly.
2. Thanks, let me try it.

[yuqisun]

For DFG mapping, there was file name changed in Mapper:
https://github.com/yuqisun/CGRA-Mapper/blob/e96becc3146ce5c98f2ecf42a0859f74d3345b6a/src/CGRA.cpp#L62

ifstream paramCGRA("./param.json");
if (!paramCGRA.good()) {
  cout<<"Parameterizable CGRA design/mapping requires paramCGRA.json"<<endl;
  return;
}
json param;
paramCGRA >> param;

in commit: yuqisun/CGRA-Mapper@2cfc7f7#diff-f1e96b93e3cc47051a6c9e2300ba678e86c648ddff8b913c1e804f8216d8d99dR62

After revert, DFG generated, but map failed, will check further.

opt-12 out:  b''
opt-12 err:  b'*** reach target loop ID: 0\n... done detected loops.size(): 1\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** current basic block: ; First Inst:   %4 = load float, float* %1, align 4, !tbaa !2\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because instruction "  %4 = load float, float* %1, align 4, !tbaa !2" is out of the scope (target loop).\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because instruction "  br label %5" is out of the scope (target loop).\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because basic block "" is out of the scope (target loop).\n\xe2\x94\x82\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** current basic block: ; First Inst:   %6 = phi float [ %4, %3 ], [ %13, %5 ]\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %6 = phi float [ %4, %3 ], [ %13, %5 ]" (ID: 0)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %7 = phi i64 [ 0, %3 ], [ %14, %5 ]" (ID: 1)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %8 = getelementptr inbounds float, float* %0, i64 %7" (ID: 2)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %9 = load float, float* %8, align 4, !tbaa !2" (ID: 3)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %10 = getelementptr inbounds float, float* %2, i64 %7" (ID: 4)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %11 = load float, float* %10, align 4, !tbaa !2" (ID: 5)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %12 = fmul float %9, %11" (ID: 6)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %13 = fadd float %6, %12" (ID: 7)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  store float %13, float* %1, align 4, !tbaa !2" (ID: 8)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %14 = add nuw nsw i64 %7, 1" (ID: 9)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  %15 = icmp eq i64 %14, 32" (ID: 10)\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ "  br i1 %15, label %16, label %5, !llvm.loop !6" (ID: 11)\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ basic block "" got ID: 0\n\xe2\x94\x82\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** current basic block: ; First Inst:   ret void\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because instruction "  ret void" is out of the scope (target loop).\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignored by pass because basic block "" is out of the scope (target loop).\n\xe2\x94\x82\n\xe2\x94\x82\n\xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** curBB: ; First Inst:   %6 = phi float [ %4, %3 ], [ %13, %5 ]\n\xe2\x94\x82   \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 *** find terminator instruction of curBB:   br i1 %15, label %16, label %5, !llvm.loop !6\n\xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 *** ignore sucBB ""\n\xe2\x94\x82   \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 *** into sucBB ""\n\xe2\x94\x82   \xe2\x94\x82   \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 Type: first inst of a BB.\n\xe2\x94\x82   \xe2\x94\x82   \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 ctrl flow point to:   %6 = phi float [ %4, %3 ], [ %13, %5 ]; In BB: \n\xe2\x94\x82   \xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ construct ctrl flow:   br i1 %15, label %16, label %5, !llvm.loop !6->  %6 = phi float [ %4, %3 ], [ %13, %5 ]\n\xe2\x94\x82   \xe2\x94\x82   \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 Type: inst without [intra-basicblock & intra-iteration data flow] nor [ctrl flow] pointed to it.\n\xe2\x94\x82   \xe2\x94\x82   \xe2\x94\x9c\xe2\x94\x80\xe2\x94\x80 ctrl flow point to:   %7 = phi i64 [ 0, %3 ], [ %14, %5 ]; In BB: \n\xe2\x94\x82   \xe2\x94\x82   \xe2\x94\x94\xe2\x94\x80\xe2\x94\x80 +++ construct ctrl flow:   br i1 %15, label %16, label %5, !llvm.loop !6->  %7 = phi i64 [ 0, %3 ], [ %14, %5 ]\n[detected one cycle] head:   %6 = phi float [ %4, %3 ], [ %13, %5 ]\ncycle edge: {  %6 = phi float [ %4, %3 ], [ %13, %5 ]  } -> {  %13 = fadd float %6, %12  } (0 -> 7)\ncycle edge: {  %13 = fadd float %6, %12  } -> {  %6 = phi float [ %4, %3 ], [ %13, %5 ]  } (7 -> 0)\n[detected one cycle] head:   %7 = phi i64 [ 0, %3 ], [ %14, %5 ]\ncycle edge: {  %7 = phi i64 [ 0, %3 ], [ %14, %5 ]  } -> {  %14 = add nuw nsw i64 %7, 1  } (1 -> 9)\ncycle edge: {  %14 = add nuw nsw i64 %7, 1  } -> {  %7 = phi i64 [ 0, %3 ], [ %14, %5 ]  } (9 -> 1)\n[detected one cycle] head:   %7 = phi i64 [ 0, %3 ], [ %14, %5 ]\ncycle edge: {  %7 = phi i64 [ 0, %3 ], [ %14, %5 ]  } -> {  %14 = add nuw nsw i64 %7, 1  } (1 -> 9)\ncycle edge: {  %14 = add nuw nsw i64 %7, 1  } -> {  %15 = icmp eq i64 %14, 32  } (9 -> 10)\ncycle edge: {  %15 = icmp eq i64 %14, 32  } -> {  br i1 %15, label %16, label %5, !llvm.loop !6  } (10 -> 11)\ncycle edge: {  br i1 %15, label %16, label %5, !llvm.loop !6  } -> {  %7 = phi i64 [ 0, %3 ], [ %14, %5 ]  } (11 -> 1)\n(9)   %14 = add nuw nsw i64 %7, 1, level: 0\n(10)   %15 = icmp eq i64 %14, 32, level: 1\n(11)   br i1 %15, label %16, label %5, !llvm.loop !6, level: 2\n(1)   %7 = phi i64 [ 0, %3 ], [ %14, %5 ], level: 3\n(2)   %8 = getelementptr inbounds float, float* %0, i64 %7, level: 4\n(4)   %10 = getelementptr inbounds float, float* %2, i64 %7, level: 4\n(3)   %9 = load float, float* %8, align 4, !tbaa !2, level: 5\n(5)   %11 = load float, float* %10, align 4, !tbaa !2, level: 5\n(6)   %12 = fmul float %9, %11, level: 6\n(7)   %13 = fadd float %6, %12, level: 7\n(0)   %6 = phi float [ %4, %3 ], [ %13, %5 ], level: 8\n(8)   store float %13, float* %1, align 4, !tbaa !2, level: 8\n'
2025-07-01 16:46:01,587 - DEBUG - STREAM b'IHDR' 16 13
2025-07-01 16:46:01,587 - DEBUG - STREAM b'bKGD' 41 6
2025-07-01 16:46:01,587 - DEBUG - b'bKGD' 41 6 (unknown)
2025-07-01 16:46:01,587 - DEBUG - STREAM b'IDAT' 59 8192
mkdir: cannot create directory ‘kernel’: File exists
/usr/lib/python3.10/subprocess.py:961: RuntimeWarning: line buffering (buffering=1) isn't supported in binary mode, the default buffer size will be used
  self.stdout = io.open(c2pread, 'rb', bufsize)
/usr/lib/python3.10/subprocess.py:966: RuntimeWarning: line buffering (buffering=1) isn't supported in binary mode, the default buffer size will be used
  self.stderr = io.open(errread, 'rb', bufsize)
mkdir: cannot create directory ‘kernel’: File exists
mkdir: cannot create directory ‘kernel’: File exists

[tancheng]

Thanks for debugging this @yuqisun, @MeowMJ changed the file name some time ago. For the current issue, I didn't see it before, it still seems like some integration issue rather than the mapper itself.

[yuqisun]

Place&Route clk_period 100000 10 hours, still running ...

[tancheng]

what about keeping 2x2 (4 tiles in total) but remove most functional units (just keep the adder)?

[yuqisun]

Using: FuList = [MemUnitRTL, AdderRTL] with set clk_period 1000000, stuck in the same step:
[INFO GRT-0101] Running extra iterations to remove overflow.

CPU still 100%, memory high, looks it's still running but just very very slow?

[tancheng]

How could those M1-M9 data exactly same? You sure the FUs are correctly passed into the Tile? You can check the generated Verilog contains MulRTL or not.

[yuqisun]

I'm using [MemUnitRTL, AdderRTL] from the beginning, only change clk period this time, so may same? Let me double check the verilog.

[yuqisun]

A new line log here! But looks it is marked as hard benchmark.

[yuqisun]

Hi @tancheng ,

P&R failed after 77+ hours as heavy routing congestion here, the worst part got 19 overflow, attached log snippet and whole congestion report below. And double checked verilog, it is using MemUnitRTL, AdderRTL FU and NahRTL (as it will be added by default: https://github.com/tancheng/VectorCGRA/blob/bddd1d500ddd5d93d3c65710161a95979980c180/fu/flexible/FlexibleFuRTL.py#L30-L31)

if NahRTL not in FuList:
  FuList.append(NahRTL)

Do you think it's good to build our agent base on the last available image (20241028), so we can simultaneously accumulate data and fix this multi-cgra p&r issue.

MemUnitRTL, AdderRTL and NahRTL FU in verilog(verilog file is attached below):

6110         MemUnitRTL__97863668881510e1 fu__0(
6111                 .clk(fu__clk[0]),
6112                 .reset(fu__reset[0]),
6113                 .from_mem_rdata__msg(fu__from_mem_rdata__msg[0]),
6114                 .from_mem_rdata__rdy(fu__from_mem_rdata__rdy[0]),
6115                 .from_mem_rdata__val(fu__from_mem_rdata__val[0]),
6116                 .recv_const__msg(fu__recv_const__msg[0]),
6117                 .recv_const__rdy(fu__recv_const__rdy[0]),
6118                 .recv_const__val(fu__recv_const__val[0]),
6119                 .recv_in__msg(fu__recv_in__msg[0]),
6120                 .recv_in__rdy(fu__recv_in__rdy[0]),
6121                 .recv_in__val(fu__recv_in__val[0]),
6122                 .recv_opt__msg(fu__recv_opt__msg[0]),
6123                 .recv_opt__rdy(fu__recv_opt__rdy[0]),
6124                 .recv_opt__val(fu__recv_opt__val[0]),
6125                 .recv_predicate__msg(fu__recv_predicate__msg[0]),
6126                 .recv_predicate__rdy(fu__recv_predicate__rdy[0]),
6127                 .recv_predicate__val(fu__recv_predicate__val[0]),
6128                 .send_out__msg(fu__send_out__msg[0]),
6129                 .send_out__rdy(fu__send_out__rdy[0]),
6130                 .send_out__val(fu__send_out__val[0]),
6131                 .to_mem_raddr__msg(fu__to_mem_raddr__msg[0]),
6132                 .to_mem_raddr__rdy(fu__to_mem_raddr__rdy[0]),
6133                 .to_mem_raddr__val(fu__to_mem_raddr__val[0]),
6134                 .to_mem_waddr__msg(fu__to_mem_waddr__msg[0]),
6135                 .to_mem_waddr__rdy(fu__to_mem_waddr__rdy[0]),
6136                 .to_mem_waddr__val(fu__to_mem_waddr__val[0]),
6137                 .to_mem_wdata__msg(fu__to_mem_wdata__msg[0]),
6138                 .to_mem_wdata__rdy(fu__to_mem_wdata__rdy[0]),
6139                 .to_mem_wdata__val(fu__to_mem_wdata__val[0])
6140         );
6141         AdderRTL__97863668881510e1 fu__1(
6142                 .clk(fu__clk[1]),
6143                 .reset(fu__reset[1]),
6144                 .from_mem_rdata__msg(fu__from_mem_rdata__msg[1]),
6145                 .from_mem_rdata__rdy(fu__from_mem_rdata__rdy[1]),
6146                 .from_mem_rdata__val(fu__from_mem_rdata__val[1]),
6147                 .recv_const__msg(fu__recv_const__msg[1]),
6148                 .recv_const__rdy(fu__recv_const__rdy[1]),
6149                 .recv_const__val(fu__recv_const__val[1]),
6150                 .recv_in__msg(fu__recv_in__msg[1]),
6151                 .recv_in__rdy(fu__recv_in__rdy[1]),
6152                 .recv_in__val(fu__recv_in__val[1]),
6153                 .recv_opt__msg(fu__recv_opt__msg[1]),
6154                 .recv_opt__rdy(fu__recv_opt__rdy[1]),
6155                 .recv_opt__val(fu__recv_opt__val[1]),
6156                 .recv_predicate__msg(fu__recv_predicate__msg[1]),
6157                 .recv_predicate__rdy(fu__recv_predicate__rdy[1]),
6158                 .recv_predicate__val(fu__recv_predicate__val[1]),
6159                 .send_out__msg(fu__send_out__msg[1]),
6160                 .send_out__rdy(fu__send_out__rdy[1]),
6161                 .send_out__val(fu__send_out__val[1]),
6162                 .to_mem_raddr__msg(fu__to_mem_raddr__msg[1]),
6163                 .to_mem_raddr__rdy(fu__to_mem_raddr__rdy[1]),
6164                 .to_mem_raddr__val(fu__to_mem_raddr__val[1]),
6165                 .to_mem_waddr__msg(fu__to_mem_waddr__msg[1]),
6166                 .to_mem_waddr__rdy(fu__to_mem_waddr__rdy[1]),
6167                 .to_mem_waddr__val(fu__to_mem_waddr__val[1]),
6168                 .to_mem_wdata__msg(fu__to_mem_wdata__msg[1]),
6169                 .to_mem_wdata__rdy(fu__to_mem_wdata__rdy[1]),
6170                 .to_mem_wdata__val(fu__to_mem_wdata__val[1])
6171         );
6172         NahRTL__97863668881510e1 fu__2(
6173                 .clk(fu__clk[2]),
6174                 .reset(fu__reset[2]),
6175                 .from_mem_rdata__msg(fu__from_mem_rdata__msg[2]),
6176                 .from_mem_rdata__rdy(fu__from_mem_rdata__rdy[2]),
6177                 .from_mem_rdata__val(fu__from_mem_rdata__val[2]),
6178                 .recv_const__msg(fu__recv_const__msg[2]),
6179                 .recv_const__rdy(fu__recv_const__rdy[2]),
6180                 .recv_const__val(fu__recv_const__val[2]),
6181                 .recv_in__msg(fu__recv_in__msg[2]),
6182                 .recv_in__rdy(fu__recv_in__rdy[2]),
6183                 .recv_in__val(fu__recv_in__val[2]),
6184                 .recv_opt__msg(fu__recv_opt__msg[2]),
6185                 .recv_opt__rdy(fu__recv_opt__rdy[2]),
6186                 .recv_opt__val(fu__recv_opt__val[2]),
6187                 .recv_predicate__msg(fu__recv_predicate__msg[2]),
6188                 .recv_predicate__rdy(fu__recv_predicate__rdy[2]),
6189                 .recv_predicate__val(fu__recv_predicate__val[2]),
6190                 .send_out__msg(fu__send_out__msg[2]),
6191                 .send_out__rdy(fu__send_out__rdy[2]),
6192                 .send_out__val(fu__send_out__val[2]),
6193                 .to_mem_raddr__msg(fu__to_mem_raddr__msg[2]),
6194                 .to_mem_raddr__rdy(fu__to_mem_raddr__rdy[2]),
6195                 .to_mem_raddr__val(fu__to_mem_raddr__val[2]),
6196                 .to_mem_waddr__msg(fu__to_mem_waddr__msg[2]),
6197                 .to_mem_waddr__rdy(fu__to_mem_waddr__rdy[2]),
6198                 .to_mem_waddr__val(fu__to_mem_waddr__val[2]),
6199                 .to_mem_wdata__msg(fu__to_mem_wdata__msg[2]),
6200                 .to_mem_wdata__rdy(fu__to_mem_wdata__rdy[2]),
6201                 .to_mem_wdata__val(fu__to_mem_wdata__val[2])
6202         );

Overflow:

violation type: Horizontal congestion
        srcs: net:ctrl_ring/routers__3/switch_units__1/mux/_00392_ net:ctrl_ring/routers__3/switch_units__1/mux/_01583_ net:ctrl_ring/routers__3/switch_units__1/mux/_01712_ net:ctrl_ring/routers__3/switch_units__1/mux/_02062_ net:ctrl_ring/routers__3/switch_units__1/mux/_02377_ net:ctrl_ring/routers__3/switch_units__1/mux/_02783_ net:ctrl_ring/routers__3/switch_units__1/mux/_03671_ net:ctrl_ring/routers__3/switch_units__1/mux/_06107_ net:ctrl_ring/routers__3/switch_units__1/mux/_06147_ net:ctrl_ring/routers__3/switch_units__1/mux/_06582_ net:ctrl_ring/routers__3/switch_units__1/mux/_06600_ net:ctrl_ring/routers__3/switch_units__1/mux/_06679_ net:ctrl_ring/routers__3/switch_units__1/mux/_07316_ net:ctrl_ring/routers__3/switch_units__1/mux/_07338_ net:ctrl_ring/routers__3/switch_units__1/mux/_07738_ net:ctrl_ring/routers__3/switch_units__1/mux/_07822_ net:ctrl_ring/routers__3/switch_units__1/mux/_08013_ net:ctrl_ring/routers__3/switch_units__1/mux/_08431_ net:ctrl_ring/routers__3/switch_units__1/mux/_08700_ net:ctrl_ring/routers__3/switch_units__1/mux/_10062_ net:ctrl_ring/routers__3/switch_units__1/mux/_10277_ net:ctrl_ring/routers__3/switch_units__1/mux/_10706_ net:ctrl_ring/routers__3/switch_units__1/mux/_11417_ net:ctrl_ring/routers__3/switch_units__1/mux/_13507_ net:ctrl_ring/routers__3/switch_units__1/mux/_13514_ net:ctrl_ring/routers__3/switch_units__1/mux/_13798_ net:ctrl_ring/routers__3/switch_units__1/mux/_17374_ net:ctrl_ring/routers__3/switch_units__1/mux/_17384_ net:ctrl_ring/routers__3/switch_units__1/mux/_18332_ net:ctrl_ring/routers__3/switch_units__1/mux/_18835_ net:ctrl_ring/routers__3/switch_units__1/mux/_18997_ net:ctrl_ring/routers__3/switch_units__1/mux/_19614_ net:ctrl_ring/routers__3/switch_units__1/mux/_20278_ net:ctrl_ring/routers__3/switch_units__1/mux/_20552_ net:ctrl_ring/routers__3/switch_units__1/mux/_20787_ net:ctrl_ring/routers__3/switch_units__1/mux/_21450_
        congestion information: capacity:17 usage:36 overflow:19

P&R Error:

[INFO GRT-0101] Running extra iterations to remove overflow.
[INFO GRT-0103] Extra Run for hard benchmark.
[INFO GRT-0197] Via related to pin nodes: 7623393
[INFO GRT-0198] Via related Steiner nodes: 652971
[INFO GRT-0199] Via filling finished.
[INFO GRT-0111] Final number of vias: 19699115
[INFO GRT-0112] Final usage 3D: 94238336
[ERROR GRT-0119] Routing congestion too high. Check the congestion heatmap in the GUI and load ./reports/asap7/CgraTemplateRTL/base/congestion.rpt in the DRC viewer.
Error: global_route.tcl, 111 GRT-0119
Command exited with non-zero status 1
Elapsed time: 77:53:31[h:]min:sec. CPU time: user 280362.41 sys 24.65 (99%). Peak memory: 24204688KB.
make[1]: *** [Makefile:827: do-5_1_grt] Error 1
make: *** [Makefile:825: results/asap7/CgraTemplateRTL/base/5_1_grt.odb] Error 2
OpenROAD 9b28074f5d04c68a9ddcc5c571583c1950e326a2
Features included (+) or not (-): +Charts +GPU +GUI +Python : None
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[ERROR ORD-0007] /WORK_REPO/CGRA-Flow/tools/OpenROAD-flow-scripts/flow/results/asap7/CgraTemplateRTL/base/6_final.odb does not exist.
Error: cmd.tcl, 1 ORD-0007

congestion.rpt: https://1drv.ms/u/c/a058f5f4a512f5b9/ERueZ7cusdZHsyYHUBdQTWQBxLDR2ltEAQq12LczjQ9PGA?e=yDQAq5

Verilog: CgraTemplateRTL.v.txt

[yuqisun]

Thanks, let me try it.

[yuqisun]

Oops, -layer is not a known keyword or flag, let me try some others after agent tool ready.

==========================================================================
cts final report_design_area
--------------------------------------------------------------------------
Design area 182729 u^2 37% utilization.
Elapsed time: 53:51.27[h:]min:sec. CPU time: user 3222.86 sys 8.26 (99%). Peak memory: 10400664KB.
cp ./results/asap7/CgraTemplateRTL/base/4_1_cts.odb ./results/asap7/CgraTemplateRTL/base/4_cts.odb
Running global_route.tcl, stage 5_1_grt
[INFO ORD-0030] Using 20 thread(s).
[ERROR STA-0562] set_global_routing_layer_adjustment -layer is not a known keyword or flag.
Error: global_route.tcl, 116 STA-0562
Command exited with non-zero status 1
Elapsed time: 0:04.19[h:]min:sec. CPU time: user 3.48 sys 0.70 (99%). Peak memory: 1724220KB.
make[1]: *** [Makefile:827: do-5_1_grt] Error 1
make: *** [Makefile:825: results/asap7/CgraTemplateRTL/base/5_1_grt.odb] Error 2
OpenROAD 9b28074f5d04c68a9ddcc5c571583c1950e326a2
Features included (+) or not (-): +Charts +GPU +GUI +Python : None
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[ERROR ORD-0007] /WORK_REPO/CGRA-Flow/tools/OpenROAD-flow-scripts/flow/results/asap7/CgraTemplateRTL/base/6_final.odb does not exist.
Error: cmd.tcl, 1 ORD-0007

[tancheng]

Hi @yuqisun, any update on this?

[yuqisun]

Failed as deepseek provides invalid configuration, change and running again now.

[tancheng]

What configuration we are trying to place with now?