angry ranting!

[josef2600]

either i am going crazy, or i am crazy!
i don't understand, what kind of clocking is this? on ov5640, in the esp driver, we have this:
set_pll(sensor,/*pll_bypass*/ false,/*pll_multiplier*/ sys_mul,/*pll_sys_div*/ 4,/*pre_div*/ 2,/*root_2x*/ false,/*pclk_root_div*/ 2,/*pclk_manual*/ true,/*pclk_div*/ 4);
and then we have this:

  float pll_pre_div2x_map[] = { 1, 1, 2, 3, 4, 1.5, 6, 2.5, 8};
  int pll_pclk_root_div_map[] = { 1, 2, 4, 8 };
  float pll_pre_div = pll_pre_div2x_map[pre_div];
  int root_2x_div = root_2x ? 2:1;
  int pll_pclk_root_div = pll_pclk_root_div_map[pclk_root_div];
  int REFIN = xclk / pll_pre_div;
  int VCO = REFIN * pll_multiplier / root_2x_div;
  int PLL_CLK = (VCO / pll_sys_div * 2 / 5);//5 here is 10bit mode / 2, for 8bit it should be 4 (reg 0x3034)
  int PCLK = PLL_CLK / pll_pclk_root_div / ((pclk_manual && pclk_div)?pclk_div:2);
  int SYSCLK = PLL_CLK / 4;

or in full, we have these:

static int calc_sysclk(int xclk, bool pll_bypass, int pll_multiplier, int pll_sys_div, int pre_div, bool root_2x, int pclk_root_div, bool pclk_manual, int pclk_div)
{
    const float pll_pre_div2x_map[] = { 1, 1, 2, 3, 4, 1.5, 6, 2.5, 8};
    const int pll_pclk_root_div_map[] = { 1, 2, 4, 8 };

    if(!pll_sys_div) {
        pll_sys_div = 1;
    }

    float pll_pre_div = pll_pre_div2x_map[pre_div];
    unsigned int root_2x_div = root_2x ? 2:1;
    unsigned int pll_pclk_root_div = pll_pclk_root_div_map[pclk_root_div];

    unsigned int REFIN = xclk / pll_pre_div;

    unsigned int VCO = REFIN * pll_multiplier / root_2x_div;

    unsigned int PLL_CLK = pll_bypass ? (xclk):(VCO / pll_sys_div * 2 / 5);//5 here is 10bit mode / 2, for 8bit it should be 4 (reg 0x3034)

    unsigned int PCLK = PLL_CLK / pll_pclk_root_div / ((pclk_manual && pclk_div)?pclk_div:2);

    unsigned int SYSCLK = PLL_CLK / 4;

    ESP_LOGI(TAG, "Calculated XVCLK: %d Hz, REFIN: %u Hz, VCO: %u Hz, PLL_CLK: %u Hz, SYSCLK: %u Hz, PCLK: %u Hz", xclk, REFIN, VCO, PLL_CLK, SYSCLK, PCLK);
    return SYSCLK;
}

static int set_pll(sensor_t *sensor, bool bypass, uint8_t multiplier, uint8_t sys_div, uint8_t pre_div, bool root_2x, uint8_t pclk_root_div, bool pclk_manual, uint8_t pclk_div){
    int ret = 0;
    if(multiplier > 252 || multiplier < 4 || sys_div > 15 || pre_div > 8 || pclk_div > 31 || pclk_root_div > 3){
        ESP_LOGE(TAG, "Invalid arguments");
        return -1;
    }
    if(multiplier > 127){
        multiplier &= 0xFE;//only even integers above 127
    }
    ESP_LOGI(TAG, "Set PLL: bypass: %u, multiplier: %u, sys_div: %u, pre_div: %u, root_2x: %u, pclk_root_div: %u, pclk_manual: %u, pclk_div: %u", bypass, multiplier, sys_div, pre_div, root_2x, pclk_root_div, pclk_manual, pclk_div);

    calc_sysclk(sensor->xclk_freq_hz, bypass, multiplier, sys_div, pre_div, root_2x, pclk_root_div, pclk_manual, pclk_div);

    ret = write_reg(sensor->slv_addr, 0x3039, bypass?0x80:0x00);
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3034, 0x1A);//10bit mode
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3035, 0x01 | ((sys_div & 0x0f) << 4));
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3036, multiplier & 0xff);
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3037, (pre_div & 0xf) | (root_2x?0x10:0x00));
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3108, (pclk_root_div & 0x3) << 4 | 0x06);
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3824, pclk_div & 0x1f);
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x460C, pclk_manual?0x22:0x20);
    }
    if (ret == 0) {
        ret = write_reg(sensor->slv_addr, 0x3103, 0x13);// system clock from pll, bit[1]
    }
    if(ret){
        ESP_LOGE(TAG, "set_sensor_pll FAILED!");
    }
    return ret;
}

and in other part, in a nutshell, we have this:

//10MHz PCLK
uint8_t sys_mul = 200;
ret = set_pll(sensor, false, sys_mul, 4, 2, false, 2, true, 4);

but, i don't get it!
and After trying the various combinations, reading various documentations spread around the net, and from the various feedback, the clock tree is probably as follows:

/*
 *   +--------------+
 *   |  Ext. Clock  |
 *   +-+------------+
 *     |  +----------+
 *     +->|   PLL1   | - reg 0x3036, for the multiplier
 *        +-+--------+ - reg 0x3037, bits 0-3 for the pre-divider
 *          |  +--------------+
 *          +->| System Clock |  - reg 0x3035, bits 4-7
 *             +-+------------+
 *               |  +--------------+
 *               +->| MIPI Divider | - reg 0x3035, bits 0-3
 *               |  +-+------------+
 *               |    +----------------> MIPI SCLK
 *               |    +  +-----+
 *               |    +->| / 2 |-------> MIPI BIT CLK
 *               |       +-----+
 *               |  +--------------+
 *               +->| PLL Root Div | - reg 0x3037, bit 4
 *                  +-+------------+
 *                    |  +---------+
 *                    +->| Bit Div | - reg 0x3034, bits 0-3
 *                       +-+-------+
 *                         |  +-------------+
 *                         +->| SCLK Div    | - reg 0x3108, bits 0-1
 *                         |  +-+-----------+
 *                         |    +---------------> SCLK
 *                         |  +-------------+
 *                         +->| SCLK 2X Div | - reg 0x3108, bits 2-3
 *                         |  +-+-----------+
 *                         |    +---------------> SCLK 2X
 *                         |  +-------------+
 *                         +->| PCLK Div    | - reg 0x3108, bits 4-5
 *                            ++------------+
 *                             +  +-----------+
 *                             +->|   P_DIV   | - reg 0x3035, bits 0-3
 *                                +-----+-----+
 *                                       +------------> PCLK
 *
 * There seems to be also constraints:
 *  - the PLL pre-divider output rate should be in the 6-27MHz range
 *  - the PLL multiplier output rate should be in the 500-800MHz range
 *  - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG
 */

and then they say you have to use 24MHz for input clock to get the full range clock working to get maximum frame rate. if so, why the fuck they are dividing the input clock??? first divide by 2 and then by 4? am i crazy? what am i missing? while creating 24MHz clock is so hard and unstable.

[josef2600]

what the hell! right?
so, now Let's break this down:

1. External Clock (XCLK): This is typically provided by your microcontroller or other external source. For the OV5640, this can be 24MHz.
2. Phase-Locked Loop (PLL): The external clock goes into the PLL to generate higher frequencies. In your case, it's multiplied by a factor defined in your set_pll function.
3. System Clock (SYSCLK): This clock is used internally by the sensor and is derived from the PLL clock.
4. Pixel Clock (PCLK): This is the clock rate at which pixel data is read out from the sensor.

The external clock (XCLK) is first divided by a pre-defined value to ensure the input to the PLL is within a specific range (6-27MHz).
Simplified Clock Tree Explanation:

1. **External Clock (XCLK)**
2. **Pre-Divider**: Divides XCLK (e.g., 24MHz / 2 = 12MHz)
3. **PLL**: Multiplies the pre-divided clock (e.g., 12MHz * 200 = 2400MHz)
4. **System Clock (SYSCLK)**: Divides PLL output (e.g., 2400MHz / 4 = 600MHz)
5. **PCLK Root Divider**: Divides SYSCLK (e.g., 600MHz / 2 = 300MHz)
6. **PCLK Final Divider**: Further divides to get final PCLK (e.g., 300MHz / 4 = 75MHz)

Constraints:

PLL Input (Pre-Divider Output): Must be 6-27MHz.
PLL Output (VCO): Must be 500-800MHz.

Calculation:

If XCLK = 24MHz:
Pre-Div = 2 => 24MHz / 2 = 12MHz (within range).
PLL Multiplier = 200 => 12MHz * 200 = 2400MHz (VCO).
PLL Sys Div = 4 => 2400MHz / 4 = 600MHz (SYSCLK).
PCLK Root Div = 2 => 600MHz / 2 = 300MHz.
PCLK Div = 4 => 300MHz / 4 = 75MHz (PCLK).

Are you kidding me? 2400MHz (VCO) !!! no wonder it is on fire!