[Feature Request]: Past port declaration as signals declaration

[wimille]

Hi,

First of all, thank you for the great job you've done on this extension. It is very pleasant to use it when you develop in VHDL.

I've a question:
Is it possible to have some features similar to those in th vhdl plugin in SublimeText ? Especially the fonctionality which allows us to copy a module port declaration and past it as signal, or component.

[richjyoung]

Thank you for the feedback!

It is my intention to add a number of features like this, all of which require a VHDL parser. Once this is in place then extracting declarations becomes much easier.

[droerich]

@richjyoung Are you planning to write your own parser or will you use an existing one? ghdl comes to mind...

[richjyoung]

I'm interested to see where the ghdl language server project goes, it is certainly a more mature and stable solution than I could build here. I'm certainly in no rush to convert this project to a language server.

On the flip side, ghdl is a not an error-tolerant parser which is pretty key for syntax highlighting. The language server extension development recommends building tolerant parsers, and for this reason Microsoft wrote their own tolerant PHP parser.

[droerich]

I totally agree, the ghdl language server is quite interesting and probably hard to beat when it comes to syntax checking and linting. However, your extension is much better with respect to syntax highlighting, I really like what you've done here.