Merge branch 'main' of github.com:os-fpga/Raptor into task/EDA-3335/restructure_editing_tool

Author: behzadmehmood

.github/workflows/main.yml

@@ -181,7 +181,7 @@ jobs:
             echo "2nd compilation" && rm -rvf build/FOEDAG_rs
             make install MONACO_EDITOR=1 CPU_CORES=2 $run_test PRODUCTION_BUILD=1 PREFIX=/opt/instl_dir PRODUCTION_DEVICES=$p_device STICK_RELEASE_VERSION=$r_d
             [ $? != 0 ] && exit 1
-            tar -czf build.tar.gz projects  \
+            tar -czf build.tar.gz projects build/Backend/OpenFPGA/vtr-verilog-to-routing/libs/libencrypt/encrypt \
             ./build/OPENLM_DIR/licensecc/extern/license-generator/src/license_generator/lccgen \
             Raptor_Tools/Create_Raptor_Artifact Raptor_Tools/Install_Raptor_Artifact /opt/instl_dir 
 
@@ -487,6 +487,7 @@ jobs:
         image: ghcr.io/${{ github.repository_owner }}/raptor:centos7latest
         options: -v ${{ github.workspace }}:/work
         run: |
+            export CI=true
             source /opt/rh/devtoolset-11/enable  
             cd work && tar -xzf build.tar.gz && rm build.tar.gz && ls -la && ls -l build 
             run_test=`cat TEST_ON`
@@ -500,27 +501,25 @@ jobs:
             cd /work/Raptor_Tools/Create_Raptor_Artifact && bash create_release.sh  -C -w  /work/opt/instl_dir
             ls -l /work/Raptor_Tools/upload/*
 
-    # The below section upload Raptor binaries to FTP so to enable it make sure provide your credentials.
-    - name: Check FTP server status
-      if: "${{ env.FORK_REPO  == 'ON' }}"
-      uses: appleboy/ssh-action@master
-      with:
-        host: ${{ secrets.FTP_IP }}
-        username: ${{ secrets.FTP_USER }}
-        key: ${{ secrets.FTP_KEY }}
-        port: ${{ secrets.FTP_PORT }}
-        script: whoami
+    # The below section upload Raptor Production binaries to release area. Make sure to provide your credentials.
+    - name: Stage the release area
+      if: "${{ env.FORK_REPO  == 'ON' && github.ref == 'refs/heads/main' }}"
+      run: |
+            cd .github/bin
+            bash productionBuild_deploy.sh  "$STAGE_REPO"
+            tag=`cat pass_tag`
+            echo "TAG=$tag" >>  $GITHUB_ENV
+      env:
+          STAGE_REPO: ${{ secrets.StageRepo }}
 
-    - name: Deploy
-      if: "${{ env.FORK_REPO  == 'ON' }}"
-      uses: appleboy/scp-action@master
-      with:
-         host: ${{ secrets.FTP_IP }}
-         username: ${{ secrets.FTP_USER }}
-         key: ${{ secrets.FTP_KEY }}
-         port: ${{ secrets.FTP_PORT }}
-         source: "./Raptor_Tools/upload/*"
-         target: "/home/rsbuilder/Raptor"
+    - name: Append Release
+      if: "${{ env.FORK_REPO  == 'ON' && github.ref == 'refs/heads/main' }}"
+      uses: softprops/action-gh-release@v2
+      with:
+          repository: os-fpga/RaptorProBuilds
+          token: ${{ secrets.StageRepo }}
+          tag_name: ${{ env.TAG }}
+          files: "./Raptor_Tools/upload/*/*"      
 
   # Reference: https://github.com/eyllanesc/69108420/blob/main/.github/workflows/test.yml
   msys2-gcc:

CMakeLists.txt

@@ -290,7 +290,7 @@ add_subdirectory(IP_Catalog)
 # Raptor version
 set(VERSION_MAJOR 1)
 set(VERSION_MINOR 2)
-set(VERSION_PATCH 34)
+set(VERSION_PATCH 39)
 
 execute_process(COMMAND git config --global --add safe.directory ${CMAKE_CURRENT_SOURCE_DIR}
   COMMAND git rev-parse --short HEAD

FOEDAG_rs

@@ -139,11 +139,12 @@ Tcl commands (Available in GUI or Batch console or Batch script):
      -no_adder                  : Do not infer adders
      -inferred_io               : Automatic I/O inference (Default false for eFPGA)
      -no_inferred_io            : No automatic I/O inference (Default true for FPGA)
-     -read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
-       0                        : Initialize register by '0' (default)
-       1                        : Initialize register by '1'
-       2                        : Leave register unintialized
-   set_limits <type> <int>    : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
+     -no_sat                  : Disable SAT solver
+     -init_registers <int>    : Force initialization of uninitialized registers
+       0                      : '0' value means initialize with '0' (Default '0' is used)
+       1                      : '1' value means initialize with '1'
+       2                      : '2' value means leave it uninitialized
+  set_limits <type> <int>     : Sets a user limit on object of type (dsp, bram), specify 0 to disable block inferrence
        dsp                    : Maximum number of usable DSPs
        bram                   : Maximum number of usable BRAMs
        carry_length           : Maximum carry length

IP_Catalog

@@ -130,11 +130,11 @@ Tcl commands (Available in GUI or Batch console or Batch script):
      -no_adder                  : Do not infer adders
      -inferred_io               : Automatic I/O inference (Default false for eFPGA)
      -no_inferred_io            : No automatic I/O inference (Default true for FPGA)
-     -read_init_registers <int> : Force initialization to uninitialized registers (0, 1, 2)
-       0                        : Initialize register by '0' (default)
-       1                        : Initialize register by '1'
-       2                        : Leave register unintialized
-<engineering>
+     -no_sat                  : Disable SAT solver
+     -init_registers <int>    : Force initialization of uninitialized registers
+       0                      : '0' value means initialize with '0' (Default '0' is used)
+       1                      : '1' value means initialize with '1'
+       2                      : '2' value means leave it uninitialized<engineering>
      -clke_strategy <strategy>: Clock enable extraction strategy for FFs:
        early                  : Perform early extraction
        late                   : Perform late extraction

README.md

@@ -120,6 +120,19 @@
                 "stepVal": 1,
                 "arg": "carry_chain_limit"
             },
+            "init_registers_spinbox_ex": {
+                "label": "Init Registers",
+                "widgetType": "spinbox",
+                "minVal": 0,
+                "maxVal": 2,
+                "stepVal": 1,
+                "arg": "init_registers"
+            },
+            "no_sat_checkbox": {
+                "label": "No Sat",
+                "widgetType": "checkbox",
+                "arg": "no_sat"
+            },
             "fast_checkbox": {
                 "label": "Fast Synthesis",
                 "widgetType": "checkbox",