University of Strathclyde - Software Defined Radio Research Laboratory
Users following strath-sdr
BANOTH BALU
banothbalu
FPGA Design & Validation Engineer | RTL Coding in VHDL & Verilog | Vivado | System Integration & Debugging | Digital Board Validation | DSP
RFMW Innovations Lab Private Limited Hyderabad Hyderabad
Marshall Al Karim
marshallexperiment
Ex-Geomatics eng, Right now I'm Majored in Comp Eng. I'm Interested in HFT FPGA, Comp. Vision is just for fun.
Matias Bolaños
bmatiasruben
Lic. in physics from University of La Plata, Argentina. PhD in physics student at Università deglu Studi di Padova.
None Italy
Dmitry Ryabikov
RDSik
Saint Petersburg State University of Telecommunications Saint Petersburg, Russia
Hailong Gong
TommyGong08
ANU 25' VCOMP | BIT 22' CS | HPC & AI Innovator
Australian National University Canberra
Shawn McSorley
Shawn-McSorley
PhD Candidate in Astrophotonics at UWA
@ICRAR-Astrophotonics-FSO Perth WA
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