@@ -192,8 +192,9 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
192192 ) {
193193 trace ! ( "collecting intra-block copies: {vreg}" ) ;
194194
195- let mut last_canonical_range : Option < ( LiveRange , CopySourceAssignment ) > = None ;
195+ let class = self . lir . vreg_class ( vreg ) ;
196196
197+ let mut last_canonical_range: Option < ( LiveRange , CopySourceAssignment ) > = None ;
197198 for & range in ranges {
198199 let range_assignment = self . get_range_assignment ( range) ;
199200 let range_data = & self . live_ranges [ range] ;
@@ -227,7 +228,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
227228 copies,
228229 instr,
229230 ParallelCopyPhase :: Before ,
230- self . lir . vreg_class ( last_range_data . vreg ) ,
231+ class ,
231232 last_assignment,
232233 range_assignment,
233234 ) ;
@@ -249,8 +250,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
249250
250251 debug_assert ! ( !source. is_reg( ) , "spill/reload to/from register" ) ;
251252
252- let spill_range_data = & self . live_ranges [ spill_range] ;
253- let spill_prog_range = spill_range_data. prog_range ;
253+ let spill_prog_range = self . live_ranges [ spill_range] . prog_range ;
254254
255255 debug_assert ! ( spill_prog_range. contains( prog_range) ) ;
256256
@@ -265,9 +265,6 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
265265 // operands.
266266 debug_assert ! ( range_instr. needs_reg( ) ) ;
267267
268- let vreg = spill_range_data. vreg ;
269- let class = self . lir . vreg_class ( vreg) ;
270-
271268 if range_instr. is_def ( ) {
272269 // We should never have any spill connectors for rematerializable defs: those
273270 // instructions should be killed entirely during spilling.
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