Rename AssignmentCopySource to CopySourceAssignment

This aligns better with `OperandAssignment` and just sounds better to me
now.

Author: nmraz

crates/codegen/src/emit.rs

@@ -5,7 +5,7 @@ use crate::{
     code_buffer::{CodeBlob, CodeBuffer, Label},
     lir::Lir,
     machine::MachineEmit,
-    regalloc::{Assignment, AssignmentCopySource, InstrOrCopy},
+    regalloc::{Assignment, CopySourceAssignment, InstrOrCopy},
 };
 
 pub type BlockLabelMap = SecondaryMap<Block, Label>;
@@ -44,10 +44,10 @@ pub fn emit_code<M: MachineEmit>(
                     );
                 }
                 InstrOrCopy::Copy(copy) => match copy.from {
-                    AssignmentCopySource::Operand(from) => {
+                    CopySourceAssignment::Operand(from) => {
                         machine.emit_copy(&mut state, &mut buffer, from, copy.to)
                     }
-                    AssignmentCopySource::Remat(instr) => machine.emit_instr(
+                    CopySourceAssignment::Remat(instr) => machine.emit_instr(
                         &mut state,
                         &mut buffer,
                         &block_labels,

crates/codegen/src/regalloc.rs

@@ -31,7 +31,7 @@ mod test_utils;
 
 pub use display::{DisplayAssignment, DisplayOperandAssignment};
 pub use types::{
-    AssignmentCopy, AssignmentCopySource, BlockExitGhostCopy, OperandAssignment, SpillSlot,
+    AssignmentCopy, BlockExitGhostCopy, CopySourceAssignment, OperandAssignment, SpillSlot,
     SpillSlotData, TaggedAssignmentCopy,
 };
 

crates/codegen/src/regalloc/display.rs

@@ -14,7 +14,7 @@ use crate::{
     machine::MachineCore,
 };
 
-use super::{types::AssignmentCopySource, Assignment, InstrOrCopy, OperandAssignment};
+use super::{types::CopySourceAssignment, Assignment, InstrOrCopy, OperandAssignment};
 
 pub struct DisplayOperandAssignment<M: MachineCore> {
     pub(super) assignment: OperandAssignment,
@@ -32,14 +32,14 @@ impl<M: MachineCore> fmt::Display for DisplayOperandAssignment<M> {
 
 pub struct DisplayAssignmentCopySource<'a, M: MachineCore> {
     pub(super) lir: &'a Lir<M>,
-    pub(super) source: AssignmentCopySource,
+    pub(super) source: CopySourceAssignment,
 }
 
 impl<M: MachineCore> fmt::Display for DisplayAssignmentCopySource<'_, M> {
     fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
         match self.source {
-            AssignmentCopySource::Operand(assignment) => write!(f, "{}", assignment.display::<M>()),
-            AssignmentCopySource::Remat(instr) => write!(f, "{:?}", self.lir.instr_data(instr)),
+            CopySourceAssignment::Operand(assignment) => write!(f, "{}", assignment.display::<M>()),
+            CopySourceAssignment::Remat(instr) => write!(f, "{:?}", self.lir.instr_data(instr)),
         }
     }
 }

crates/codegen/src/regalloc/parallel_copy.rs

@@ -3,7 +3,7 @@ use smallvec::{smallvec, SmallVec};
 use crate::lir::{Instr, PhysReg};
 
 use super::{
-    types::{AssignmentCopy, AssignmentCopySource, ParallelCopy},
+    types::{AssignmentCopy, CopySourceAssignment, ParallelCopy},
     OperandAssignment, SpillSlot,
 };
 
@@ -21,7 +21,7 @@ pub fn resolve(
     let mut operands = SmallVec::<[OperandAssignment; 16]>::new();
 
     for copy in parallel_copies {
-        if let AssignmentCopySource::Operand(from) = copy.from {
+        if let CopySourceAssignment::Operand(from) = copy.from {
             operands.push(from);
         }
         operands.push(copy.to);
@@ -36,7 +36,7 @@ pub fn resolve(
     for copy in parallel_copies {
         let to = find_operand(&operands, copy.to);
         match copy.from {
-            AssignmentCopySource::Operand(from) => {
+            CopySourceAssignment::Operand(from) => {
                 let from = find_operand(&operands, from);
                 debug_assert!(
                     copy_sources[to].is_none(),
@@ -45,7 +45,7 @@ pub fn resolve(
 
                 copy_sources[to] = Some(TrackedCopySource::Operand(from as u32));
             }
-            AssignmentCopySource::Remat(instr) => {
+            CopySourceAssignment::Remat(instr) => {
                 copy_sources[to] = Some(TrackedCopySource::Remat(instr));
             }
         }
@@ -84,7 +84,7 @@ pub fn resolve(
                             TrackedCopySource::Remat(instr) => {
                                 // Remats always terminate the current chain as they can never be
                                 // copied out of a different assignment.
-                                ctx.emit(AssignmentCopySource::Remat(instr), operands[operand]);
+                                ctx.emit(CopySourceAssignment::Remat(instr), operands[operand]);
                                 break;
                             }
                         }
@@ -109,7 +109,7 @@ pub fn resolve(
 
                     // Insert the final copy out of the temporary here (resolved assignments are in
                     // reverse order).
-                    ctx.emit(AssignmentCopySource::Operand(tmp_op), operands[prev]);
+                    ctx.emit(CopySourceAssignment::Operand(tmp_op), operands[prev]);
 
                     break;
                 }
@@ -130,15 +130,15 @@ pub fn resolve(
             if let Some(src) = last_copy_src {
                 let from = operands[src];
                 let to = operands[operand];
-                ctx.emit(AssignmentCopySource::Operand(from), to);
+                ctx.emit(CopySourceAssignment::Operand(from), to);
             }
 
             match copy_cycle_break {
                 Some((cycle_operand, tmp_op)) if cycle_operand == operand => {
                     // We've found the start of a broken parallel copy cycle - make sure the
                     // original value of `operand` is saved before it is overwritten by the copy
                     // inserted above.
-                    ctx.emit(AssignmentCopySource::Operand(operands[operand]), tmp_op);
+                    ctx.emit(CopySourceAssignment::Operand(operands[operand]), tmp_op);
                 }
                 _ => {}
             }
@@ -214,7 +214,7 @@ impl<'s, S: RegScavenger> ResolvedCopyContext<'s, S> {
         }
     }
 
-    fn emit(&mut self, from: AssignmentCopySource, to: OperandAssignment) {
+    fn emit(&mut self, from: CopySourceAssignment, to: OperandAssignment) {
         if from.is_reg() || to.is_reg() {
             // Copies involving at least one register can be performed directly.
             self.emit_raw(from, to);
@@ -231,7 +231,7 @@ impl<'s, S: RegScavenger> ResolvedCopyContext<'s, S> {
 
                         // Restore the original value of `tmp_reg` from the emergency spill.
                         self.emit_raw(
-                            AssignmentCopySource::Operand(OperandAssignment::Spill(
+                            CopySourceAssignment::Operand(OperandAssignment::Spill(
                                 emergency_spill,
                             )),
                             OperandAssignment::Reg(tmp_reg),
@@ -242,7 +242,7 @@ impl<'s, S: RegScavenger> ResolvedCopyContext<'s, S> {
                 };
 
             self.emit_raw(
-                AssignmentCopySource::Operand(OperandAssignment::Reg(tmp_reg)),
+                CopySourceAssignment::Operand(OperandAssignment::Reg(tmp_reg)),
                 to,
             );
             self.emit_raw(from, OperandAssignment::Reg(tmp_reg));
@@ -251,14 +251,14 @@ impl<'s, S: RegScavenger> ResolvedCopyContext<'s, S> {
                 // If we're using an emergency spill, back up the original value of `tmp_reg` before
                 // using it.
                 self.emit_raw(
-                    AssignmentCopySource::Operand(OperandAssignment::Reg(tmp_reg)),
+                    CopySourceAssignment::Operand(OperandAssignment::Reg(tmp_reg)),
                     OperandAssignment::Spill(emergency_spill),
                 );
             }
         }
     }
 
-    fn emit_raw(&mut self, from: AssignmentCopySource, to: OperandAssignment) {
+    fn emit_raw(&mut self, from: CopySourceAssignment, to: OperandAssignment) {
         self.copies.push(AssignmentCopy { from, to });
     }
 }
@@ -352,7 +352,7 @@ mod tests {
         };
 
         for copy in &parallel_copies {
-            if let AssignmentCopySource::Operand(OperandAssignment::Reg(from)) = copy.from {
+            if let CopySourceAssignment::Operand(OperandAssignment::Reg(from)) = copy.from {
                 scavenger.used_regs.insert(from);
             }
             if let OperandAssignment::Reg(to) = copy.to {

crates/codegen/src/regalloc/redundant_copy.rs

@@ -1,7 +1,7 @@
 use fx_utils::FxHashMap;
 use smallvec::SmallVec;
 
-use super::{types::AssignmentCopySource, AssignmentCopy, OperandAssignment};
+use super::{types::CopySourceAssignment, AssignmentCopy, OperandAssignment};
 
 #[derive(Debug, Clone, Copy, PartialEq, Eq)]
 pub enum RedundantCopyVerdict {
@@ -11,8 +11,8 @@ pub enum RedundantCopyVerdict {
 
 #[derive(Default)]
 pub struct RedundantCopyTracker {
-    copy_sources: FxHashMap<OperandAssignment, AssignmentCopySource>,
-    copy_targets: FxHashMap<AssignmentCopySource, SmallVec<[OperandAssignment; 4]>>,
+    copy_sources: FxHashMap<OperandAssignment, CopySourceAssignment>,
+    copy_targets: FxHashMap<CopySourceAssignment, SmallVec<[OperandAssignment; 4]>>,
 }
 
 impl RedundantCopyTracker {
@@ -27,7 +27,7 @@ impl RedundantCopyTracker {
 
     pub fn process_copy(&mut self, copy: &AssignmentCopy) -> RedundantCopyVerdict {
         let from = match copy.from {
-            AssignmentCopySource::Operand(from) => self.assignment_source(from),
+            CopySourceAssignment::Operand(from) => self.assignment_source(from),
             from => from,
         };
         let to = self.assignment_source(copy.to);
@@ -50,19 +50,19 @@ impl RedundantCopyTracker {
     fn remove_copies_from(&mut self, assignment: OperandAssignment) {
         if let Some(targets) = self
             .copy_targets
-            .remove(&AssignmentCopySource::Operand(assignment))
+            .remove(&CopySourceAssignment::Operand(assignment))
         {
             for target in targets {
                 self.copy_sources.remove(&target);
             }
         }
     }
 
-    fn assignment_source(&self, assignment: OperandAssignment) -> AssignmentCopySource {
+    fn assignment_source(&self, assignment: OperandAssignment) -> CopySourceAssignment {
         self.copy_sources
             .get(&assignment)
             .copied()
-            .unwrap_or(AssignmentCopySource::Operand(assignment))
+            .unwrap_or(CopySourceAssignment::Operand(assignment))
     }
 }
 

crates/codegen/src/regalloc/reify.rs

@@ -23,7 +23,7 @@ use super::{
     parallel_copy::{self, RegScavenger},
     redundant_copy::{RedundantCopyTracker, RedundantCopyVerdict},
     types::{
-        AssignmentCopySource, BlockExitGhostCopy, InstrSlot, LiveRange, ParallelCopies,
+        BlockExitGhostCopy, CopySourceAssignment, InstrSlot, LiveRange, ParallelCopies,
         ParallelCopy, ParallelCopyPhase, ProgramPoint, TaggedAssignmentCopy,
     },
     Assignment, InstrAssignmentData, OperandAssignment, SpillSlot, SpillSlotData,
@@ -38,7 +38,7 @@ struct BlockParamEdgeKey {
     to_vreg: VirtReg,
 }
 
-type BlockParamOutMap = FxHashMap<BlockParamEdgeKey, (VirtReg, AssignmentCopySource)>;
+type BlockParamOutMap = FxHashMap<BlockParamEdgeKey, (VirtReg, CopySourceAssignment)>;
 
 struct BlockParamIn {
     block: Block,
@@ -53,10 +53,10 @@ fn record_parallel_copy(
     instr: Instr,
     phase: ParallelCopyPhase,
     class: RegClass,
-    from: AssignmentCopySource,
+    from: CopySourceAssignment,
     to: OperandAssignment,
 ) {
-    if from != AssignmentCopySource::Operand(to) {
+    if from != CopySourceAssignment::Operand(to) {
         copies.push(ParallelCopy {
             instr,
             phase,
@@ -153,7 +153,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                 Instr::new(0),
                 ParallelCopyPhase::Before,
                 self.lir.vreg_class(block_param),
-                AssignmentCopySource::Operand(OperandAssignment::Reg(preg)),
+                CopySourceAssignment::Operand(OperandAssignment::Reg(preg)),
                 assignment,
             );
         }
@@ -193,8 +193,8 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
     ) {
         trace!("collecting intra-block copies: {vreg}");
 
-        let mut cur_spill: Option<(LiveRange, AssignmentCopySource)> = None;
-        let mut last_canonical_range: Option<(LiveRange, AssignmentCopySource)> = None;
+        let mut cur_spill: Option<(LiveRange, CopySourceAssignment)> = None;
+        let mut last_canonical_range: Option<(LiveRange, CopySourceAssignment)> = None;
 
         for &range in ranges {
             let range_assignment = self.get_range_assignment(range);
@@ -280,7 +280,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                             instr.next(),
                             ParallelCopyPhase::Before,
                             class,
-                            AssignmentCopySource::Operand(range_assignment),
+                            CopySourceAssignment::Operand(range_assignment),
                             OperandAssignment::Spill(spill),
                         );
                     }
@@ -432,7 +432,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                     panic!("vreg {vreg} not live-out across edge {pred} -> {block}");
                 };
 
-                if pred_assignment == AssignmentCopySource::Operand(assignment) {
+                if pred_assignment == CopySourceAssignment::Operand(assignment) {
                     // Nothing to copy here, don't bother trying to figure out where.
                     continue;
                 }
@@ -553,7 +553,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                             instr.next(),
                             ParallelCopyPhase::Before,
                             self.lir.vreg_class(vreg),
-                            AssignmentCopySource::Operand(OperandAssignment::Reg(preg)),
+                            CopySourceAssignment::Operand(OperandAssignment::Reg(preg)),
                             range_assignment,
                         );
                     } else {
@@ -596,7 +596,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                                     instr,
                                     ParallelCopyPhase::PreCopy,
                                     self.lir.vreg_class(vreg),
-                                    AssignmentCopySource::Operand(range_assignment),
+                                    CopySourceAssignment::Operand(range_assignment),
                                     OperandAssignment::Reg(preg),
                                 );
                             }
@@ -609,7 +609,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                                     instr,
                                     ParallelCopyPhase::PreCopy,
                                     self.lir.vreg_class(vreg),
-                                    AssignmentCopySource::Operand(range_assignment),
+                                    CopySourceAssignment::Operand(range_assignment),
                                     def_assignment,
                                 );
                                 assignment.assign_instr_use(instr, i, def_assignment);
@@ -657,10 +657,10 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
             .expect("expected range assignment to be an operand")
     }
 
-    fn get_range_assignment(&self, range: LiveRange) -> AssignmentCopySource {
+    fn get_range_assignment(&self, range: LiveRange) -> CopySourceAssignment {
         let fragment_data = &self.live_set_fragments[self.live_ranges[range].fragment];
         match fragment_data.assignment.expand() {
-            Some(preg) => AssignmentCopySource::Operand(OperandAssignment::Reg(preg)),
+            Some(preg) => CopySourceAssignment::Operand(OperandAssignment::Reg(preg)),
             None => {
                 debug_assert!(fragment_data.flags.contains(LiveSetFragmentFlags::SPILLED));
 
@@ -670,7 +670,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                 {
                     let vreg = self.live_ranges[range].vreg;
                     let def_instr = self.remattable_vreg_defs[vreg].unwrap();
-                    return AssignmentCopySource::Remat(def_instr);
+                    return CopySourceAssignment::Remat(def_instr);
                 }
 
                 let live_set_data = &self.live_sets[fragment_data.live_set];
@@ -688,7 +688,7 @@ impl<M: MachineRegalloc> RegAllocContext<'_, M> {
                     );
                 }
 
-                AssignmentCopySource::Operand(OperandAssignment::Spill(
+                CopySourceAssignment::Operand(OperandAssignment::Spill(
                     self.live_sets[fragment_data.live_set].spill_slot.unwrap(),
                 ))
             }
@@ -846,7 +846,7 @@ impl<'a, M: MachineRegalloc> AssignedRegScavenger<'a, M> {
         // before `pos`. Destinations need to be marked as used for correct behavior with block
         // live-outs and outgoing params, which might not be live at all at `pos`.
         for copy in copies {
-            if let AssignmentCopySource::Operand(OperandAssignment::Reg(from)) = copy.from {
+            if let CopySourceAssignment::Operand(OperandAssignment::Reg(from)) = copy.from {
                 self.used_tmp_regs.insert(from);
             }
             if let OperandAssignment::Reg(to) = copy.to {